公开(公告)号：US09859221B2

公开(公告)日：2018-01-02

申请号：US14626085

申请日：2015-02-19

Applicant: IBIDEN CO., LTD.

Inventor： Toyotaka Shimabe ,  Toshiki Furutani ,  Shunsuke Sakai

IPC: H05K1/18 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H05K3/46

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/568 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/82039 ,  H01L2924/153 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09827 ,  H05K2201/09972 ,  H05K2201/10522 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A multilayer wiring board with built-in electronic components includes a substrate including an insulating material and having multiple opening portions, a first conductor layer formed on a surface of the substrate and having an opening portion such that the substrate has the opening portions inside the opening portion of the first conductor layer, multiple electronic components positioned in the opening portions of the substrate, and an insulating layer formed on the substrate such that the insulating layer is formed on the electronic components and on the first conductor layer. The opening portions are formed in the substrate such that the opening portions include two opening portions and that the substrate has a partition wall formed between the two opening portions.

公开(公告)号：US09832882B2

公开(公告)日：2017-11-28

申请号：US14480250

申请日：2014-09-08

Applicant: INKTEC Co., Ltd.

Inventor： Kwang-Choon Chung ,  Ji Hoon Yoo ,  Joonki Seong ,  Dae Sang Han ,  Nam-Boo Cho

IPC: H05K3/12 ,  H05K3/10 ,  H05K1/02 ,  H05K1/09 ,  H05K3/06

CPC classification number: H05K3/1258 ,  H05K1/095 ,  H05K3/06 ,  H05K2201/0376 ,  H05K2201/0382 ,  H05K2201/09036 ,  H05K2201/09827 ,  H05K2203/1173 ,  Y10T29/49155

Abstract: Provided herein is a conductive pattern making method and conductive pattern, the method including forming a groove such that its width in an inlet area is bigger than its width in an inner area; filling the groove with a conductive ink composition; and drying the conductive ink composition so that a solvent contained in the conductive ink composition inside the groove is volatilized to reduce the volume of the conductive ink composition.

公开(公告)号：US20170273170A1

公开(公告)日：2017-09-21

申请号：US15070838

申请日：2016-03-15

Applicant: Cisco Technology, Inc.

Inventor： Eric Nels Johnson ,  Richard Carlyle Campbell

IPC: H05K1/02 ,  H05K3/40 ,  H05K3/00 ,  H05K1/11 ,  H05K1/09

CPC classification number: H05K1/028 ,  H05K1/09 ,  H05K1/111 ,  H05K1/118 ,  H05K3/0044 ,  H05K3/0052 ,  H05K3/244 ,  H05K3/4007 ,  H05K2201/09727 ,  H05K2201/09827

Abstract: According to one aspect, an apparatus includes a substrate, a conductor, and a contact pad. The substrate has a first edge, and the conductor is formed on the substrate. The contact pad has a first end and a second end, and is formed on the substrate and connected to the conductor at the first end. The contact pad has a non-uniform configuration, the non-uniform configuration including a first width and a second width, the first width and the second width being measured with respect to a common axis, the first width being wider than a second width, the second width being a width of the contact pad at the second end, the second end being coincident with the first edge.

公开(公告)号：US09756732B2

公开(公告)日：2017-09-05

申请号：US14760982

申请日：2013-01-18

Applicant: MEIKO ELECTRONICS CO., LTD.

Inventor： Yasuaki Seki ,  Tomoyuki Nagata ,  Mitsuaki Toda

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/02 ,  H05K3/00 ,  H01L23/00 ,  H01L23/522 ,  H05K3/30 ,  H05K3/46

CPC classification number: H05K1/186 ,  H01L23/5226 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/19 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/82005 ,  H01L2224/82039 ,  H01L2224/83005 ,  H01L2224/92144 ,  H05K1/0206 ,  H05K1/0222 ,  H05K1/0298 ,  H05K1/113 ,  H05K1/114 ,  H05K1/115 ,  H05K1/185 ,  H05K1/188 ,  H05K3/0017 ,  H05K3/0035 ,  H05K3/305 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09827 ,  H05K2201/10 ,  H05K2203/063 ,  H05K2203/1461 ,  Y10T156/10

Abstract: A device embedded substrate (20), includes: an insulation layer (12) including an insulation resin material; an electric or electronic device (4) embedded in the insulation layer (12); a terminal (15) serving as an electrode included in the device (4); a conductor pattern (18) formed on the surface of the insulation layer (12); and a conducting via (21) for electrically connecting the conductor pattern (18) and the terminals (15) with each other. The conducting via (21) is made up of a large-diameter section (21a) having a large diameter and a small-diameter section (21b) having a smaller diameter than that of the large-diameter section (21a), in order starting from the conductor pattern (18) toward the terminal (15). A stepped section (17) is formed between the large-diameter section (21a) and the small-diameter section (21b). The large-diameter section (21a) is formed so as to penetrate a sheet-shaped glass cloth (11) disposed in the insulation layer (12).

公开(公告)号：US20170244184A1

公开(公告)日：2017-08-24

申请号：US15422978

申请日：2017-02-02

Applicant: MERCURY SYSTEMS, INC.

Inventor： Darryl J. MCKENNEY ,  Absu METHRATTA ,  Erica OUELLETTE

IPC: H01R12/71 ,  H05K1/02 ,  H05K1/11 ,  H01R13/405 ,  H01R13/05

CPC classification number: H01R12/58 ,  H01R4/028 ,  H01R12/00 ,  H01R12/526 ,  H01R12/714 ,  H01R12/716 ,  H01R13/05 ,  H01R13/405 ,  H01R13/652 ,  H05K1/0213 ,  H05K1/0237 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/111 ,  H05K1/112 ,  H05K1/115 ,  H05K1/181 ,  H05K1/184 ,  H05K3/308 ,  H05K3/34 ,  H05K3/3421 ,  H05K3/42 ,  H05K3/421 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/09827 ,  H05K2201/10098 ,  H05K2201/10189 ,  H05K2201/10295 ,  H05K2201/1078 ,  H05K2201/10803 ,  H05K2201/10871 ,  H05K2201/10878 ,  H05K2201/10901 ,  H05K2203/0455 ,  Y02P70/611

Abstract: According to exemplary embodiments, a tapered surface interconnect is formed on a printed circuit board (PCB). A compliant pin of an electrical connector may be coupled to the tapered surface interconnect and soldered thereto. The surface interconnect may be formed by drilling through one or more layers of the PCB. The depth of the surface interconnect may be shorter than a height or a thickness of the PCB. The surface interconnect may have a tapered side wall to allow for a better fit with a tapered compliant pin. The inclination of the side wall of the surface interconnect may be linear or concave. The intersection between the tapered sidewall and the bottom of the surface interconnect may be rounded to minimize pin insertion issues and may allow for easier solder flux evacuation. The compliant pin may be soldered into place upon being coupled to the tapered surface interconnect.

公开(公告)号：US09736939B2

公开(公告)日：2017-08-15

申请号：US14848907

申请日：2015-09-09

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Suk Hyeon Cho ,  Yong Ho Baek ,  Young Gwan Ko ,  Yoong Oh ,  Young Kuk Ko

IPC: H05K3/46 ,  H05K1/11 ,  H05K1/02 ,  H05K3/00 ,  H05K3/42

CPC classification number: H05K1/115 ,  H05K1/0271 ,  H05K3/007 ,  H05K3/422 ,  H05K3/4605 ,  H05K3/4608 ,  H05K3/4682 ,  H05K2201/09827

Abstract: A printed circuit board may include: a first circuit layer; a first insulating layer disposed on the first circuit layer; a high-rigidity layer disposed on the first insulating layer; and a second circuit layer disposed on the high-rigidity layer and connected to the first circuit layer by a first via extending through the first insulating layer and the high-rigidity layer, wherein a rigidity of the high-rigidity layer is greater than a rigidity of the first insulating layer.

公开(公告)号：US20170208692A1

公开(公告)日：2017-07-20

申请号：US15328190

申请日：2015-07-24

Applicant: LG INNOTEK CO., LTD.

Inventor： Jae Hyun AHN ,  Min Wook YU

IPC: H05K1/18 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/184 ,  H01L33/486 ,  H01L33/62 ,  H05K1/0203 ,  H05K1/0206 ,  H05K1/115 ,  H05K1/185 ,  H05K3/007 ,  H05K3/421 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10106 ,  H05K2201/10151 ,  H05K2203/1563

Abstract: A printed circuit board includes an insulating layer and an element embedded in the insulating layer and exposed through a surface of the insulating layer.

公开(公告)号：US09699919B2

公开(公告)日：2017-07-04

申请号：US15041104

申请日：2016-02-11

Applicant: Yazaki Corporation

Inventor： Akemi Maebashi ,  Pharima Akanitsuk

IPC: H05K1/14 ,  H05K3/34

CPC classification number: H05K3/3447 ,  H05K2201/09818 ,  H05K2201/09827 ,  H05K2201/09836 ,  H05K2201/09845 ,  H05K2201/10272

Abstract: An electronic component unit and a wire harness are provided with a bus bar plate. The bus bar plate is provided with a metallic bus bar that is built in a resin material, and including a through-hole in which a terminal of a relay mounted on a mounting surface is soldered. The through-hole is provided with a bus bar through-hole which penetrates the bus bar, and a resin material through-hole which penetrates the resin material and is formed to be larger than the bus bar through-hole to expose the surface of the bus bar. When an inner diameter of the bus bar through-hole is defined as r and an inner diameter of the resin material through-hole is defined as R, 1.5r≦R is satisfied.

公开(公告)号：US20170104143A1

公开(公告)日：2017-04-13

申请号：US15316028

申请日：2015-05-26

Applicant: 3M INNOVATIVE PROPERTIES COMPANY

Inventor： Ravi Palaniswamy ,  Alejandro Aldrin II Agcaoili Narag ,  Siang Sin Foo ,  Hiromitsu Kosugi

IPC: H01L33/62 ,  H01L33/58 ,  H01L33/48

CPC classification number: H01L33/62 ,  B32B7/12 ,  B32B15/08 ,  B32B27/281 ,  B32B2255/10 ,  B32B2255/20 ,  B32B2307/202 ,  B32B2457/202 ,  H01L33/486 ,  H01L33/58 ,  H01L2933/0033 ,  H01L2933/0058 ,  H01L2933/0066 ,  H05K1/0306 ,  H05K1/0346 ,  H05K1/036 ,  H05K1/189 ,  H05K3/28 ,  H05K2201/0154 ,  H05K2201/017 ,  H05K2201/0179 ,  H05K2201/09827 ,  H05K2201/09881 ,  H05K2201/10106

Abstract: Flexible LED assemblies (300) are described. More particularly, flexible LED (320) assemblies having flexible substrates (302) with conductive features (304, 306) positioned on or in the substrate, and layers of ceramic (310) positioned over exposed portions of the substrate to protect against UV degradation, as well as methods of making such assembles, are described.

公开(公告)号：US20170094801A1

公开(公告)日：2017-03-30

申请号：US15170943

申请日：2016-06-02

Applicant: ETHERTRONICS, INC.

Inventor： Seung Hyuk CHOI ,  Hyun Jun HONG ,  Tae Wook KIM ,  Cheong Ho RYU ,  Young Sang KIM ,  Sung Jun KIM

IPC: H05K3/00 ,  H05K3/42 ,  H05K3/46 ,  H05K3/18 ,  H05K3/28

CPC classification number: H05K3/0026 ,  H05K3/0014 ,  H05K3/185 ,  H05K3/188 ,  H05K3/28 ,  H05K3/423 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/09118 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2203/0582 ,  H05K2203/0588 ,  H05K2203/072 ,  H05K2203/107 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: The present disclosure relates to the method of manufacturing circuit having lamination layer using LDS (Laser Direct Structuring) to ease the application on surface structure for applied product of various electronic circuit and particularly, in which can form circuit structure of single-layer to multiple-layer on the surface of injection-molded substrate in the shape of plane or curved surface, metal product, glasses, ceramic, rubber or other material.