公开(公告)号：US20100006623A1

公开(公告)日：2010-01-14

申请号：US12560640

申请日：2009-09-16

Applicant: Bernhard P. LANGE ,  Anthony L. COYLE ,  Jeffrey Gail HOLLOWAY

Inventor： Bernhard P. LANGE ,  Anthony L. COYLE ,  Jeffrey Gail HOLLOWAY

IPC: B23K1/00

CPC classification number: H01L21/561 ,  H01L21/4821 ,  H01L23/3121 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/341 ,  H05K2201/10689 ,  H05K2201/10931 ,  H05K2201/10969 ,  H05K2201/10984 ,  Y02P70/613 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Disclosed herein is a method of manufacturing a semiconductor package with a solder standoff on lead pads that reach to the edge of the package (non-pullback leads). It includes encapsulating a plurality of die on a lead frame strip. The lead frame strip comprises a plurality of package sites, which further comprises a plurality of lead pads and a die pad. The method also includes forming a channel between the lead pads of nearby package sites without singulating the packages. Another step in the method includes disposing solder on the lead pads, the die pad, or the lead pads and the die pads without substantially covering the channel with solder. The manufacturing method further includes singulating the packages.

Abstract translation: 本文公开了一种制造半导体封装的方法，该半导体封装在引线焊盘上具有焊接位置，该焊盘抵达封装的边缘（非拉回引线）。 它包括将多个管芯封装在引线框架条上。 引线框架条包括多个封装位置，其还包括多个引线焊盘和管芯焊盘。 该方法还包括在附近的封装位置的引线焊盘之间形成通道，而不需要对封装进行分离。 该方法的另一步骤包括在焊盘，芯片焊盘或引线焊盘和裸片焊盘上布置焊料，而基本上不用焊料覆盖焊道。 制造方法还包括将包装分离。

公开(公告)号：US20090121362A1

公开(公告)日：2009-05-14

申请号：US12235739

申请日：2008-09-23

Applicant: Young-Cheol JANG

Inventor： Young-Cheol JANG

IPC: H01L21/50 ,  H01L23/498

CPC classification number: H01L23/3107 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/181 ,  H05K3/341 ,  H05K3/3442 ,  H05K2201/0373 ,  H05K2201/10931 ,  Y02P70/613 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and mounting method of improving reliability by strengthening adhesive strength of both a printed circuit board and a surface mounting package, includes a chip pad on which a semiconductor device is disposed, and lead terminals, wherein at least one of the chip pad and the lead terminals have a plurality of grooves. Accordingly, in comparison with a typical package, since a plurality of grooves are formed on both a chip pad and lead terminals of a package adhering to a printed circuit, an adhesive area of both the package and the cream solder is widened so that the shearing strength may be improved and greater solder joint reliability can be acquired.

Abstract translation: 通过增强印刷电路板和表面安装封装的粘合强度来提高可靠性的半导体封装和安装方法包括其上设置有半导体器件的芯片焊盘和引线端子，其中芯片焊盘和 引线端子具有多个槽。 因此，与典型的封装相比，由于在附接到印刷电路的封装的芯片焊盘和引线端子上形成多个槽，所以封装和膏状焊料的粘合区域变宽，使得剪切 可以提高强度并且可以获得更大的焊点可靠性。

公开(公告)号：US20080128255A1

公开(公告)日：2008-06-05

申请号：US11948507

申请日：2007-11-30

Applicant: Jean-Christophe Villain ,  Michel Cour

Inventor： Jean-Christophe Villain ,  Michel Cour

IPC: H01H13/14

CPC classification number: H05K3/303 ,  H01H2001/5888 ,  H05K3/341 ,  H05K2201/09472 ,  H05K2201/09781 ,  H05K2201/10053 ,  H05K2201/10931 ,  H05K2201/2036 ,  Y02P70/613

Abstract: An arrangement may include a substrate and an electrical component. The electrical component may include a base made of an insulating material and a plurality of connection terminals. Each connection terminal is connected to a corresponding connection pad of the substrate by means of a spot of solder paste. The arrangement may further include a block interposed between the substrate and the base of the electrical component. The block may be located substantially on the axis of application of a force for actuating the electrical component and may be designed to inhibit deformation of the base. The block may include a spot of solder paste soldered to an associated conducting pad on the substrate.

Abstract translation: 一种布置可以包括基底和电气部件。 电气部件可以包括由绝缘材料制成的基座和多个连接端子。 每个连接端子通过焊膏点连接到基板的相应的连接焊盘。 该布置还可以包括插入在基板和电气部件的基部之间的块。 该块可以基本上位于施加用于致动电气部件的力的轴线上，并且可以设计成阻止基座的变形。 块可以包括焊接到衬底上的相关联的导电焊盘的焊膏点。

公开(公告)号：US07285803B2

公开(公告)日：2007-10-23

申请号：US10911643

申请日：2004-08-05

Applicant: Hideaki Kato ,  Kanae Matsumura ,  Shunsuke Ohtsuka

Inventor： Hideaki Kato ,  Kanae Matsumura ,  Shunsuke Ohtsuka

IPC: H01L33/00

CPC classification number: H05K3/3442 ,  H01L25/0753 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K2201/10106 ,  H05K2201/1084 ,  H05K2201/10931 ,  Y02P70/613 ,  H01L2924/00014

Abstract: A notch portion 7A is disposed on a formation surface of a wiring pattern 7 and is located in a contact point with a wiring pattern 9 of an outside substrate 8, so that a solder 9a melted by reflow soldering slowly flows up along an edge of the notch portion 7A, improving a solder-joint performance. The notch portion 7A is formed in a recess shape as formed by cutting away the substrate 6 and as a result, the melted solder stays in the recess portion, which prevents the melted solder from moving up over the notch portion 7A.

Abstract translation: 切口部分7A设置在布线图案7的形成表面上并且位于与外部基板8的布线图案9的接触点中，使得通过回流焊接熔化的焊料9a沿边缘向上流动 的切口部7A，提高焊接性能。 切口部7A形成为通过切除基板6而形成的凹部形状，结果，熔融的焊料滞留在凹部中，防止熔融的焊料向上移动到切口部7A上方。

公开(公告)号：US06984881B2

公开(公告)日：2006-01-10

申请号：US10463051

申请日：2003-06-16

Applicant: Hem P. Takiar

Inventor： Hem P. Takiar

IPC: H01L23/02

CPC classification number: H05K3/3426 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/32188 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85399 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/18165 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2201/10931 ,  H05K2201/2081 ,  Y02P70/613 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Improved apparatus and methods for stacking integrated circuit packages having leads are disclosed. According to one embodiment, the leads of an integrated circuit package are exposed and provided with solder balls so that corresponding leads of another integrated circuit package being stacked thereon can be electrically connected. The stacking results in increased integrated circuit density with respect to a substrate, yet the stacked integrated circuit packages are able to still enjoy having an overall thin or low profile.

Abstract translation: 公开了用于堆叠具有引线的集成电路封装的改进的装置和方法。 根据一个实施例，集成电路封装的引线被暴露并设置有焊球，使得堆叠在其上的另一个集成电路封装的相应引线可以电连接。 堆叠导致相对于衬底的集成电路密度增加，但是堆叠的集成电路封装仍然可以享受整体薄或薄的轮廓。

公开(公告)号：US20020146863A1

公开(公告)日：2002-10-10

申请号：US09832398

申请日：2001-04-10

Inventor： Chieh-Yuan Lin ,  Jui-Yi Chuang ,  Chi-Chuan Wu

IPC: H01L021/44 ,  H01L021/48 ,  H01L021/50

CPC classification number: H05K3/341 ,  H01L2224/48091 ,  H01L2224/48247 ,  H05K1/0206 ,  H05K3/3452 ,  H05K3/3484 ,  H05K3/42 ,  H05K2201/10727 ,  H05K2201/10931 ,  H05K2201/2036 ,  H05K2203/0455 ,  Y02P70/613 ,  H01L2924/00014

Abstract: A modified SMT (Surface Mount Technology) process is proposed for mounting an exposed-pad type of semiconductor device over a PCB (printed circuit board), which can help prevent the problem of floated soldering of the semiconductor device over the PCB. By this modified SMT process, a plurality of via holes are formed in the pad-mounting area of the printed circuit board; and a solder material is pasted over the bottom end of each of the via holes. As the semiconductor device is mounted in position over the printed circuit board, a solder-reflow process is performed on the pasted solder material so as to cause the pasted solder material to be wetted to the entire surface of the solder-wettable layer in each of the via holes, thereby allowing the solder material to reflow to the upper end of each of the via holes where the reflowed solder is also wetted to the exposed die pad of the semiconductor device, thereby securely bonding the semiconductor device to the PCB.

Abstract translation: 提出了一种改进的SMT（表面贴装技术）工艺，用于在PCB（印刷电路板）上安装暴露焊盘类型的半导体器件，这有助于防止半导体器件在PCB上漂浮焊接的问题。 通过这种改进的SMT工艺，在印刷电路板的焊盘安装区域中形成多个通孔; 并且焊料材料粘贴在每个通孔的底端上。 当半导体器件安装在印刷电路板上的适当位置时，对粘贴的焊料进行焊料回流处理，以使糊状的焊料材料被润湿到每个焊料可润湿层的整个表面 通孔，从而允许焊料材料回流到每个通孔的上端，其中回流焊料也被润湿到半导体器件的裸露裸片焊盘，从而将半导体器件牢固地接合到PCB。

公开(公告)号：US5852324A

公开(公告)日：1998-12-22

申请号：US788014

申请日：1997-01-24

Applicant: Renato Poinelli ,  Mauro Mazzola

Inventor： Renato Poinelli ,  Mauro Mazzola

IPC: H01L23/50 ,  H01L21/673 ,  H01L23/31 ,  H01L23/433 ,  H05K1/02 ,  H05K3/34

CPC classification number: H05K3/341 ,  H01L23/3107 ,  H01L23/4334 ,  H01L2924/0002 ,  H05K1/0201 ,  H05K2201/10689 ,  H05K2201/10931 ,  H05K2201/10969 ,  Y02P70/613

Abstract: A QFP plastic surface-mounting semiconductor power device, comprising a plastic package inside which there is provided a chip which is connected by means of conductors to terminals that protrude from the plastic package, and a heat sink plate that is arranged on the bottom of the plastic package and has thinner ends, wherein the length of the heat sink plate is at least equal to the minimum length of the plastic package, channels being formed in the plastic package in a position that is adjacent to the thinner ends of the heat sink plate.

Abstract translation: 一种QFP塑料表面安装半导体功率器件，包括塑料封装，其中设置有通过导体连接到从塑料封装突出的端子的芯片，以及散热板，其布置在 塑料封装并且具有更薄的端部，其中散热板的长度至少等于塑料封装的最小长度，在塑料封装中形成的通道处于与散热板的较薄端部相邻的位置 。

公开(公告)号：US5045914A

公开(公告)日：1991-09-03

申请号：US663225

申请日：1991-03-01

Applicant: James J. Casto ,  Michael B. McShane ,  Paul T. Lin

Inventor： James J. Casto ,  Michael B. McShane ,  Paul T. Lin

IPC: H01L23/31 ,  H01L23/367 ,  H01L23/495 ,  H01L25/10 ,  H05K3/34

CPC classification number: H05K3/3436 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/49517 ,  H01L23/49589 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K2201/09709 ,  H05K2201/10515 ,  H05K2201/10568 ,  H05K2201/10689 ,  H05K2201/10734 ,  H05K2201/10924 ,  H05K2201/10931 ,  H05K2201/2036 ,  H05K3/3426 ,  Y02P70/613

Abstract: A pad array electronic device for mounting on a substrate, such as a printed circuit board (PCB), has a relatively rigid package body with a plurality of holes bearing connecting mechanisms for bonding to lands on the PCB. The package body may be a thermoset plastic or other material that can be injection molded around an electronic component, such as an integrated circuit (IC) bonded to a lead frame. An integrated circuit die or other electronic component is mounted in proximity with or on the lead frame and electrical connections between the integrated circuit chip and the frame are made by any conventional means. In one aspect, the substrate leads are provided at their outer ends that are exposed by holes in the package with solder balls or pads for making connections to the PCB. The package body may be optionally used to stand off the device a set distance from the PCB so that the solder balls will form the proper concave structure. The periphery of the package body may function as a carrier structure to protect the lead or connection structures during testing, handling and board mounting. The open vias permit back side testing of the device before or after mounting of the package to the PCB. Additionally, a heat sink structure and/or capacitor may be directly bonded to the side or the top of the pad array electronic device which may be used singly or in multiple, stacked configurations, to facilitate the thermal dissipation from the device.

Abstract translation: 用于安装在诸如印刷电路板（PCB）的基板上的焊盘阵列电子器件具有相对刚性的封装体，其具有多个孔，该多个孔承载用于结合到PCB上的焊盘的连接机构。 封装体可以是可以围绕电子部件注射模制的热固性塑料或其它材料，例如结合到引线框架的集成电路（IC）。 集成电路芯片或其他电子部件安装在引线框架附近或之上，并且通过任何常规方式制造集成电路芯片和框架之间的电连接。 在一个方面，衬底引线设置在其外端处，其被封装中的孔暴露以用于与PCB连接的焊球或焊盘。 封装体可以可选地用于从PCB离开设备一定距离，使得焊球将形成适当的凹形结构。 封装主体的周边可以用作载体结构，以在测试，处理和板安装期间保护引线或连接结构。 打开的通孔允许在将封装安装到PCB之前或之后对器件进行背面测试。 此外，散热器结构和/或电容器可以直接结合到可以单独使用或以多个堆叠配置使用的焊盘阵列电子器件的侧面或顶部，以便于从器件散热。

公开(公告)号：US20240040702A1

公开(公告)日：2024-02-01

申请号：US18268364

申请日：2021-09-30

Applicant: HITACHI,ASTEMO, LTD.

Inventor： Takeshi TOKUYAMA ,  Takahiro ARAKI ,  Shigehise AOYAGI

IPC: H05K1/18 ,  H01L25/18 ,  H02M7/00 ,  H01L23/495 ,  H02M7/537 ,  H01L23/00

CPC classification number: H05K1/186 ,  H01L25/18 ,  H02M7/003 ,  H05K2201/10787 ,  H05K2201/10931 ,  H05K2201/09072 ,  H05K2201/10901 ,  H01L2224/40225 ,  H01L23/49524 ,  H05K2201/10946 ,  H05K2201/10174 ,  H02M7/537 ,  H01L24/40 ,  H05K2201/10166

Abstract: A power semiconductor device includes: a circuit body having a pair of conductor parts and a power semiconductor element sandwiched between the pair of conductor parts; a substrate in which a through hole is formed; and a sealing material that seals at least a part of each of the circuit body and the substrate, in which the circuit body is inserted into the through hole and has first and second exposed surfaces exposed from the sealing material, and the substrate has, in the through hole, a first protrusion and a second protrusion that protrude toward a center of the through hole and are connected to the circuit body, the first protrusion and the second protrusion being formed at positions opposed to each other in the through hole, and at least one of the first protrusion and the second protrusion being a terminal that transmits power to the power semiconductor element.

公开(公告)号：US09844146B2

公开(公告)日：2017-12-12

申请号：US15152218

申请日：2016-05-11

Applicant: Flextronics Automotive GmbH & Co. KG

Inventor： Peter Lutz ,  Kevin Buermann

IPC: H05K1/00 ,  H05K1/18 ,  H05K3/30

CPC classification number: H05K1/189 ,  H05K3/288 ,  H05K3/305 ,  H05K3/328 ,  H05K2201/05 ,  H05K2201/0929 ,  H05K2201/10037 ,  H05K2201/10227 ,  H05K2201/1031 ,  H05K2201/10931 ,  H05K2203/0278 ,  H05K2203/04 ,  H05K2203/16

Abstract: The invention is related to an electrical circuitry assembly as well as a method for manufacturing such an electrical circuitry assembly, wherein the assembly basically but not exclusively comprising of an electrically conductive metal plate and a circuit including a conductive layer and wherein both the metal plate and the circuit shall be electrically connected to each other.