公开(公告)号：US20130143364A1

公开(公告)日：2013-06-06

申请号：US13312395

申请日：2011-12-06

Applicant: Hsiu-Jen LIN ,  Chung-Shi LIU ,  Ming-Da CHENG ,  Chun-Cheng LIN ,  Yu-Peng TSAI ,  Cheng-Ting CHEN

Inventor： Hsiu-Jen LIN ,  Chung-Shi LIU ,  Ming-Da CHENG ,  Chun-Cheng LIN ,  Yu-Peng TSAI ,  Cheng-Ting CHEN

IPC: H01L21/58

Abstract: A method includes vacuum annealing on a substrate having at least one solder bump to reduce voids at an interface of the at least one solder bump. A die is mounted over the substrate.

Abstract translation: 一种方法包括在具有至少一个焊料凸块的衬底上进行真空退火以减少在至少一个焊料凸块的界面处的空隙。 模具安装在基板上。

公开(公告)号：US20130009307A1

公开(公告)日：2013-01-10

申请号：US13179299

申请日：2011-07-08

Applicant: Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Yi-Wen Wu ,  Hsiu-Jen Lin ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

Inventor： Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Yi-Wen Wu ,  Hsiu-Jen Lin ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L24/03 ,  H01L21/566 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/3157 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/03903 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00

Abstract: A method includes forming a passivation layer over a metal pad, which is overlying a semiconductor substrate. A first opening is formed in the passivation layer, with a portion of the metal pad exposed through the first opening. A seed layer is formed over the passivation layer and to electrically coupled to the metal pad. The seed layer further includes a portion over the passivation layer. A first mask is formed over the seed layer, wherein the first mask has a second opening directly over at least a portion of the metal pad. A PPI is formed over the seed layer and in the second opening. A second mask is formed over the first mask, with a third opening formed in the second mask. A portion of a metal bump is formed in the third opening. After the step of forming the portion of the metal bump, the first and the second masks are removed.

Abstract translation: 一种方法包括在覆盖在半导体衬底上的金属焊盘上形成钝化层。 在钝化层中形成第一开口，金属垫的一部分通过第一开口暴露。 种子层形成在钝化层之上并且电耦合到金属焊盘。 种子层还包括钝化层上的部分。 在种子层上形成第一掩模，其中第一掩模具有直接在金属焊盘的至少一部分上的第二开口。 在种子层和第二开口中形成PPI。 在第一掩模上形成第二掩模，第二掩模形成在第二掩模中。 金属凸块的一部分形成在第三开口中。 在形成金属凸块的部分的步骤之后，去除第一和第二掩模。

公开(公告)号：US20120178251A1

公开(公告)日：2012-07-12

申请号：US13004376

申请日：2011-01-11

Applicant: Zheng-Yi LIM ,  Yi-Wen WU ,  Wen-Hsiung LU ,  Chih-Wei LIN ,  Tzong-Huann YANG ,  Hsiu-Jen LIN ,  Ming-Da CHENG ,  Chung-Shi LIU

Inventor： Zheng-Yi LIM ,  Yi-Wen WU ,  Wen-Hsiung LU ,  Chih-Wei LIN ,  Tzong-Huann YANG ,  Hsiu-Jen LIN ,  Ming-Da CHENG ,  Chung-Shi LIU

IPC: H01L21/768

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11824 ,  H01L2224/11827 ,  H01L2224/11849 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13583 ,  H01L2224/13693 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/01047 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01073 ,  H01L2924/01049 ,  H01L2924/0103 ,  H01L2924/01025 ,  H01L2924/01022 ,  H01L2924/01032 ,  H01L2924/01078 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01082 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The disclosure relates to fabrication of to a metal pillar. An exemplary method of fabricating a semiconductor device comprises the steps of providing a substrate having a contact pad; forming a passivation layer extending over the substrate having an opening over the contact pad; forming a metal pillar over the contact pad and a portion of the passivation layer; forming a solder layer over the metal pillar; and causing sidewalls of the metal pillar to react with an organic compound to form a self-assembled monolayer or self-assembled multi-layers of the organic compound on the sidewalls of the metal pillar.

Abstract translation: 本公开涉及制造金属柱。 制造半导体器件的示例性方法包括以下步骤：提供具有接触焊盘的衬底; 形成在衬底上延伸的钝化层，该钝化层在接触焊盘上具有开口; 在所述接触焊盘和所述钝化层的一部分上形成金属柱; 在金属柱上形成焊料层; 并且使金属柱的侧壁与有机化合物反应，以在金属柱的侧壁上形成自组装单层或有机化合物的自组装多层。

公开(公告)号：US12086103B2

公开(公告)日：2024-09-10

申请号：US17248756

申请日：2021-02-05

Applicant: Hsiu-Jen Lin

Inventor： Hsiu-Jen Lin

IPC: G06F16/16 ,  G06F3/14 ,  G07C9/00 ,  G06F3/0481

CPC classification number: G06F16/16 ,  G06F3/14 ,  G07C9/00182 ,  G06F3/0481

Abstract: An intelligent storage system and an intelligent storage method thereof are disclosed. The system includes a cabinet and loading tables, each loading table includes an accommodating groove having a shape corresponding the shape of the object to be stored, and a sensing device in the accommodating groove. A central control device includes a processor electrically connected to the sensing device, the output device and an input device, and a system database for the processor to access or store information. The sensing devices senses whether there is a corresponding stored object in each accommodating groove to form a status signal carrying an identification code, and outputs it to the processor, then the processor accesses the corresponding information in the system database according to the identification code of the status signal, so as to realize the management and status display of the stored object, and effectively improve work safety and effectiveness.

公开(公告)号：US09030022B2

公开(公告)日：2015-05-12

申请号：US13280157

申请日：2011-10-24

Applicant: Meng-Tse Chen ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Meng-Tse Chen ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L25/50 ,  H01L21/31105 ,  H01L21/565 ,  H01L22/12 ,  H01L22/20 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/1131 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A device includes a package component having conductive features on a top surface, and a polymer region molded over the top surface of the first package component. A plurality of openings extends from a top surface of the polymer region into the polymer region, wherein each of the conductive features is exposed through one of the plurality of openings. The plurality of openings includes a first opening having a first horizontal size, and a second opening having a second horizontal size different from the first horizontal size.

Abstract translation: 一种器件包括在顶表面上具有导电特征的封装元件和模塑在第一封装元件的顶表面上的聚合物区域。 多个开口从聚合物区域的顶表面延伸到聚合物区域中，其中每个导电特征通过多个开口中的一个露出。 多个开口包括具有第一水平尺寸的第一开口和具有不同于第一水平尺寸的第二水平尺寸的第二开口。

公开(公告)号：US20130334561A1

公开(公告)日：2013-12-19

申请号：US13527318

申请日：2012-06-19

Applicant: Hsiu-Jen LIN ,  Jian-Shian Lin ,  Shau-Yi Chen ,  Jen-Hui Tsai

Inventor： Hsiu-Jen LIN ,  Jian-Shian Lin ,  Shau-Yi Chen ,  Jen-Hui Tsai

IPC: H01L33/48 ,  H01L33/62

CPC classification number: H01L33/0079 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L33/0095 ,  H01L2224/2745 ,  H01L2224/27462 ,  H01L2224/29109 ,  H01L2224/29113 ,  H01L2224/83097 ,  H01L2224/83191 ,  H01L2224/83207 ,  H01L2224/8381 ,  H01L2224/83825 ,  H01L2224/8383 ,  H01L2224/94 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/351 ,  H01L2924/01083 ,  H01L2924/0105 ,  H01L2924/0103 ,  H01L2924/01049 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/27 ,  H01L2924/00

Abstract: A method for bonding an LED wafer, a method for manufacturing an LED chip, and a bonding structure are provided. The method for bonding an LED wafer includes the following steps. A first metal film is formed on an LED wafer. A second metal film is formed on a substrate. A bonding material layer whose melting point is lower than or equal to about 110° C. is formed on the surface of the first metal film. The LED wafer is placed on the substrate. The bonding material layer is heated at a pre-solid reaction temperature for a pre-solid time to perform a pre-solid reaction. The bonding material layer is heated at a diffusion reaction temperature for a diffusing time to perform a diffusion reaction, wherein the melting points of the first and the second inter-metallic layers after diffusion reaction are higher than about 110° C.

Abstract translation: 提供一种用于结合LED晶片的方法，制造LED芯片的方法和接合结构。 用于结合LED晶片的方法包括以下步骤。 在LED晶片上形成第一金属膜。 在基板上形成第二金属膜。 在第一金属膜的表面上形成熔点低于或等于约110℃的接合材料层。 将LED晶片放置在基板上。 将接合材料层在预固体反应温度下加热预固化时间以进行预固体反应。 接合材料层在扩散反应温度下加热扩散时间以进行扩散反应，其中扩散反应后第一和第二金属间层的熔点高于约110℃。

公开(公告)号：US20130115735A1

公开(公告)日：2013-05-09

申请号：US13289719

申请日：2011-11-04

Applicant: Meng-Tse Chen ,  Hsiu-Jen Lin ,  Chun-Cheng Lin ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Meng-Tse Chen ,  Hsiu-Jen Lin ,  Chun-Cheng Lin ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L21/98 ,  B29C35/08

CPC classification number: H01L24/97 ,  B29C33/68 ,  B29C43/18 ,  H01L21/563 ,  H01L21/566 ,  H01L2224/16225 ,  H01L2924/01322 ,  H01L2924/181 ,  H01L2924/00

Abstract: Methods and apparatus for a forming molded underfills. A method is disclosed including loading a flip chip substrate into a selected one of the upper mold chase and lower mold chase of a mold press at a first temperature; positioning a molded underfill material in the at least one of the upper and lower mold chases while maintaining the first temperature which is lower than a melting temperature of the molded underfill material; forming a sealed mold cavity and creating a vacuum in the mold cavity; raising the temperature of the molded underfill material to a second temperature greater than the melting point to cause the molded underfill material to flow over the flip chip substrate forming an underfill layer and forming an overmolded layer; and cooling the flip chip substrate to a third temperature substantially lower than the melting temperature of the molded underfill material. An apparatus is disclosed.

Abstract translation: 用于成型模制底部填料的方法和装置。 公开了一种方法，其包括在第一温度下将倒装芯片衬底加载到模压机的上模追逐和下模追逐中的所选择的一个中; 将模制的底部填充材料定位在上模具和下模具中的至少一个中，同时保持低于模制的底部填充材料的熔融温度的第一温度; 形成密封的模腔并在模腔中产生真空; 将模制的底部填充材料的温度提高到大于熔点的第二温度，以使模制的底部填充材料在形成底部填充层的倒装芯片衬底上流动并形成包覆成型层; 并将所述倒装芯片基板冷却至基本上低于所述模制底部填充材料的熔融温度的第三温度。 公开了一种装置。

公开(公告)号：US20120256228A1

公开(公告)日：2012-10-11

申请号：US13530396

申请日：2012-06-22

Applicant: Hsiu Jen Lin ,  Jian Shian Lin ,  Shau Yi Chen ,  Chieh Lung Lai

Inventor： Hsiu Jen Lin ,  Jian Shian Lin ,  Shau Yi Chen ,  Chieh Lung Lai

IPC: H01L33/62

CPC classification number: H01L23/53247 ,  H01L24/29 ,  H01L24/83 ,  H01L33/0079 ,  H01L33/0095 ,  H01L33/30 ,  H01L33/40 ,  H01L33/486 ,  H01L33/62 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/83193 ,  H01L2224/83207 ,  H01L2224/8382 ,  H01L2224/83825 ,  H01L2224/8383 ,  H01L2224/83948 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15724 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2933/0066 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/01083 ,  H01L2924/00014

Abstract: An LED includes a first intermetallic layer, a first metal thin film layer, an LED chip, a substrate, a second metal thin film layer, and a second intermetallic layer. The first metal thin film layer is located on the first intermetallic layer. The LED chip is located on the first metal thin film layer. The second metal thin film layer is located on the substrate. The second intermetallic layer is located on the second metal thin film layer, and the first intermetallic layer is located on the second intermetallic layer. Materials of the first and the second metal thin film layer are selected from a group consisting of Au, Ag, Cu, and Ni. Materials of the intermetallic layers are selected from a group consisting of a Cu—In—Sn intermetallics, an Ni—In—Sn intermetallics, an Ni—Bi intermetallics, an Au—In intermetallics, an Ag—In intermetallics, an Ag—Sn intermetallics, and an Au—Bi intermetallics.

Abstract translation: LED包括第一金属间层，第一金属薄膜层，LED芯片，基板，第二金属薄膜层和第二金属间层。 第一金属薄膜层位于第一金属间层上。 LED芯片位于第一金属薄膜层上。 第二金属薄膜层位于基板上。 第二金属间化合物层位于第二金属薄膜层上，第一金属间化合物层位于第二金属间层上。 第一和第二金属薄膜层的材料选自由Au，Ag，Cu和Ni组成的组。 金属间层的材料选自Cu-In-Sn金属间化合物，Ni-In-Sn金属间化合物，Ni-Bi金属间化合物，Au-In金属间化合物，Ag-In金属间化合物，Ag-Sn 金属间化合物和Au-Bi金属间化合物。

公开(公告)号：US08236687B2

公开(公告)日：2012-08-07

申请号：US12854278

申请日：2010-08-11

Applicant: Hsiu-Jen Lin ,  Jian-Shian Lin ,  Shau-Yi Chen ,  Chieh-Lung Lai

Inventor： Hsiu-Jen Lin ,  Jian-Shian Lin ,  Shau-Yi Chen ,  Chieh-Lung Lai

IPC: H01L21/44

CPC classification number: H01L23/53247 ,  H01L24/29 ,  H01L24/83 ,  H01L33/0079 ,  H01L33/0095 ,  H01L33/30 ,  H01L33/40 ,  H01L33/486 ,  H01L33/62 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/83193 ,  H01L2224/83207 ,  H01L2224/8382 ,  H01L2224/83825 ,  H01L2224/8383 ,  H01L2224/83948 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15724 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2933/0066 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/01083 ,  H01L2924/00014

Abstract: A die-bonding method is suitable for die-bonding a LED chip having a first metal thin-film layer to a substrate. The method includes forming a second metal thin film layer on a surface of the substrate; forming a die-bonding material layer on the second metal thin film layer; placing the LED chip on the die-bonding material layer with the first metal thin film layer contacting the die-bonding material layer; heating the die-bonding material layer at a liquid -solid reaction temperature for a pre-curing time, so as to form a first intermetallic layer and a second intermetallic layer; and heating the die-bonding material layer at a solid-solid reaction temperature for a curing time for performing a solid-solid reaction. The liquid-solid reaction temperature and the solid-solid reaction temperature are both lower than 110° C., and a melting point of the first and second intermetallic layers after the solid-solid reaction is higher than 200° C.

Abstract translation: 芯片接合方法适合于将具有第一金属薄膜层的LED芯片芯片接合到基板上。 该方法包括在基板的表面上形成第二金属薄膜层; 在所述第二金属薄膜层上形成芯片接合材料层; 将第一金属薄膜层与芯片接合材料层接触，将LED芯片放置在芯片接合材料层上; 在液固固化反应温度下加热芯片接合材料层达预固化时间，以形成第一金属间层和第二金属间层; 并在固 - 固反应温度下加热芯片接合材料层进行固 - 固反应的固化时间。 液固反应温度和固 - 固反应温度均低于110℃，固 - 固反应后第一和第二金属间化合物的熔点高于200℃。