公开(公告)号：US20130181338A1

公开(公告)日：2013-07-18

申请号：US13349405

申请日：2012-01-12

Applicant: Wen-Hsiung Lu ,  Yi-Wen Wu ,  Chih-Wei Lin ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Wen-Hsiung Lu ,  Yi-Wen Wu ,  Chih-Wei Lin ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/498 ,  H01L21/20

CPC classification number: H01L23/3192 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/03823 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05008 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05548 ,  H01L2224/05564 ,  H01L2224/05567 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/10126 ,  H01L2224/11464 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/73104 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A structure comprises a post passivation interconnect layer formed over a semiconductor substrate, a metal bump formed over the post passivation interconnect layer and a molding compound layer formed over the semiconductor substrate. A lower portion of the metal bump is embedded in the molding compound layer and a middle portion of the metal bump is surrounded by a concave meniscus molding compound protection layer.

Abstract translation: 一种结构包括形成在半导体衬底上的后钝化互连层，形成在后钝化互连层上的金属凸块和形成在半导体衬底上的模塑复合层。 金属凸块的下部嵌入在模塑料层中，并且金属凸块的中间部分被凹弯月面模塑料保护层包围。

公开(公告)号：US20130122652A1

公开(公告)日：2013-05-16

申请号：US13298056

申请日：2011-11-16

Applicant: Hsiu-Jen Lin ,  Chih-Wei Lin ,  Cheng-Ting Chen ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Hsiu-Jen Lin ,  Chih-Wei Lin ,  Cheng-Ting Chen ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L21/50

CPC classification number: H01L24/75 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/75283 ,  H01L2224/7598 ,  H01L2224/81005 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/8123 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/81

Abstract: A method includes placing a cover over a lower package component, wherein the cover comprises an opening aligned to the lower package component. An upper package component is placed over the lower package component. The upper package component is aligned to the opening, and a solder region is dispose between the upper package component and the lower package component. The cover and the upper package component are exposed to a radiation to reflow the solder region.

Abstract translation: 一种方法包括将盖子放置在下部封装部件上，其中盖子包括与下部封装部件对准的开口。 上封装组件放置在下封装组件上。 上部封装部件与开口对准，并且焊接区域配置在上部封装部件和下部封装部件之间。 盖和上部封装部件暴露于辐射以回流焊接区域。

公开(公告)号：US20130099385A1

公开(公告)日：2013-04-25

申请号：US13280157

申请日：2011-10-24

Applicant: Meng-Tse Chen ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Meng-Tse Chen ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/538 ,  H01L21/66

CPC classification number: H01L25/50 ,  H01L21/31105 ,  H01L21/565 ,  H01L22/12 ,  H01L22/20 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/1131 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A device includes a package component having conductive features on a top surface, and a polymer region molded over the top surface of the first package component. A plurality of openings extends from a top surface of the polymer region into the polymer region, wherein each of the conductive features is exposed through one of the plurality of openings. The plurality of openings includes a first opening having a first horizontal size, and a second opening having a second horizontal size different from the first horizontal size.

公开(公告)号：US20130062761A1

公开(公告)日：2013-03-14

申请号：US13228768

申请日：2011-09-09

Applicant: Chih-Wei Lin ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Hsiu-Jen Lin ,  Bor-Ping Jang ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu ,  Meng-Tse Chen ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Kuei-Wei Huang ,  Wei-Hung Lin

Inventor： Chih-Wei Lin ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Hsiu-Jen Lin ,  Bor-Ping Jang ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu ,  Meng-Tse Chen ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Kuei-Wei Huang ,  Wei-Hung Lin

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/52 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68377 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06515 ,  H01L2224/09181 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/9202 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15322 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00

Abstract: Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.

公开(公告)号：US20130005055A1

公开(公告)日：2013-01-03

申请号：US13543418

申请日：2012-07-06

Applicant: Jian-Shian Lin ,  Chieh-Lung Lai ,  Hsiu-Jen Lin ,  Weng-Jung Lu ,  Yi-Ping Huang ,  Ya-Chun Tu

Inventor： Jian-Shian Lin ,  Chieh-Lung Lai ,  Hsiu-Jen Lin ,  Weng-Jung Lu ,  Yi-Ping Huang ,  Ya-Chun Tu

IPC: H01L33/62

CPC classification number: F21V19/02 ,  F21K9/00 ,  F21Y2107/50 ,  F21Y2115/10 ,  H01L25/0753 ,  H01L33/62 ,  H01L2224/29339 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/01047 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01014

Abstract: A light-emitting diode (LED) module and an LED packaging method. As the LED module is packaged under the consideration of candela distribution, each of the lead frames of the LED chips packaged in the LED module is bended for tilting the LED chips by different angles to exhibit various lighting effects. Meanwhile, in the LED packaging method, a plurality of LED chips can be loaded on board rapidly and aligned by one operation to result in less deviation in the candela distribution curve.

Abstract translation: 一种发光二极管（LED）模块和一种LED封装方法。 由于LED模块在考虑到烛光分布的情况下被封装，所以封装在LED模块中的LED芯片的每个引线框架被弯曲以使LED芯片以不同的角度倾斜以呈现各种照明效果。 同时，在LED封装方法中，可以通过一次操作快速地将多个LED芯片加载在一起，从而导致烛光分布曲线的偏差较小。

公开(公告)号：US20120322255A1

公开(公告)日：2012-12-20

申请号：US13161303

申请日：2011-06-15

Applicant: Ming-Da Cheng ,  Chih-Wei Lin ,  Hsiu-Jen Lin ,  Tzong-Hann Yang ,  Wen-Hsiung Lu ,  Zheng-Yi Lim ,  Yi-Wen Wu ,  Chung-Shi Liu

Inventor： Ming-Da Cheng ,  Chih-Wei Lin ,  Hsiu-Jen Lin ,  Tzong-Hann Yang ,  Wen-Hsiung Lu ,  Zheng-Yi Lim ,  Yi-Wen Wu ,  Chung-Shi Liu

IPC: H01L21/768

CPC classification number: H01L24/11 ,  H01L21/6836 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68327 ,  H01L2224/11003 ,  H01L2224/111 ,  H01L2224/1133 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/13655 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81193 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2224/11

Abstract: A system and method for forming metal bumps is provided. An embodiment comprises attaching conductive material to a carrier medium and then contacting the conductive material to conductive regions of a substrate. Portions of the conductive material are then bonded to the conductive regions using a bonding process to form conductive caps on the conductive regions, and residual conductive material and the carrier medium are removed. A reflow process is used to reflow the conductive caps into conductive bumps.

Abstract translation: 提供一种用于形成金属凸块的系统和方法。 一个实施例包括将导电材料附着到载体介质上，然后将导电材料接触到基底的导电区域。 然后使用接合工艺将导电材料的部分结合到导电区域，以在导电区域上形成导电盖，并且去除残留的导电材料和载体介质。 回流工艺用于将导电盖重新流到导电凸块中。

公开(公告)号：US08242011B2

公开(公告)日：2012-08-14

申请号：US13004376

申请日：2011-01-11

Applicant: Zheng-Yi Lim ,  Yi-Wen Wu ,  Wen-Hsiung Lu ,  Chih-Wei Lin ,  Tzong-Huann Yang ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Zheng-Yi Lim ,  Yi-Wen Wu ,  Wen-Hsiung Lu ,  Chih-Wei Lin ,  Tzong-Huann Yang ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L21/44

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11824 ,  H01L2224/11827 ,  H01L2224/11849 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13583 ,  H01L2224/13693 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/01047 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01073 ,  H01L2924/01049 ,  H01L2924/0103 ,  H01L2924/01025 ,  H01L2924/01022 ,  H01L2924/01032 ,  H01L2924/01078 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01082 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The disclosure relates to fabrication of to a metal pillar. An exemplary method of fabricating a semiconductor device comprises the steps of providing a substrate having a contact pad; forming a passivation layer extending over the substrate having an opening over the contact pad; forming a metal pillar over the contact pad and a portion of the passivation layer; forming a solder layer over the metal pillar; and causing sidewalls of the metal pillar to react with an organic compound to form a self-assembled monolayer or self-assembled multi-layers of the organic compound on the sidewalls of the metal pillar.

Abstract translation: 本公开涉及制造金属柱。 制造半导体器件的示例性方法包括以下步骤：提供具有接触焊盘的衬底; 形成在所述衬底上延伸的钝化层，所述钝化层在所述接触焊盘上具有开口; 在所述接触焊盘和所述钝化层的一部分上形成金属柱; 在金属柱上形成焊料层; 并且使金属柱的侧壁与有机化合物反应，以在金属柱的侧壁上形成自组装单层或有机化合物的自组装多层。

公开(公告)号：US20210263890A1

公开(公告)日：2021-08-26

申请号：US17248756

申请日：2021-02-05

Applicant: Hsiu-Jen Lin

Inventor： Hsiu-Jen Lin

IPC: G06F16/16 ,  G06F3/14 ,  G07C9/00

Abstract: An intelligent storage system and an intelligent storage method thereof are disclosed. The system includes a cabinet and loading tables, each loading table includes an accommodating groove having a shape corresponding the shape of the object to be stored, and a sensing device in the accommodating groove. A central control device includes a processor electrically connected to the sensing device, the output device and an input device, and a system database for the processor to access or store information. The sensing devices senses whether there is a corresponding stored object in each accommodating groove to form a status signal carrying an identification code, and outputs it to the processor, then the processor accesses the corresponding information in the system database according to the identification code of the status signal, so as to realize the management and status display of the stored object, and effectively improve work safety and effectiveness.

公开(公告)号：US09412717B2

公开(公告)日：2016-08-09

申请号：US13289719

申请日：2011-11-04

Applicant: Meng-Tse Chen ,  Hsiu-Jen Lin ,  Chun-Cheng Lin ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Meng-Tse Chen ,  Hsiu-Jen Lin ,  Chun-Cheng Lin ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L21/00 ,  H01L23/00 ,  B29C43/18 ,  H01L21/56 ,  B29C33/68

CPC classification number: H01L24/97 ,  B29C33/68 ,  B29C43/18 ,  H01L21/563 ,  H01L21/566 ,  H01L2224/16225 ,  H01L2924/01322 ,  H01L2924/181 ,  H01L2924/00

Abstract: Methods and apparatus for a forming molded underfills. A method is disclosed including loading a flip chip substrate into a selected one of the upper mold chase and lower mold chase of a mold press at a first temperature; positioning a molded underfill material in the at least one of the upper and lower mold chases while maintaining the first temperature which is lower than a melting temperature of the molded underfill material; forming a sealed mold cavity and creating a vacuum in the mold cavity; raising the temperature of the molded underfill material to a second temperature greater than the melting point to cause the molded underfill material to flow over the flip chip substrate forming an underfill layer and forming an overmolded layer; and cooling the flip chip substrate to a third temperature substantially lower than the melting temperature of the molded underfill material. An apparatus is disclosed.

Abstract translation: 用于成型模制底部填料的方法和装置。 公开了一种方法，其包括在第一温度下将倒装芯片衬底加载到模压机的上模追逐和下模追逐中的所选择的一个中; 将模制的底部填充材料定位在上模具和下模具中的至少一个中，同时保持低于模制的底部填充材料的熔融温度的第一温度; 形成密封的模腔并在模腔中产生真空; 将模制的底部填充材料的温度提高到大于熔点的第二温度，以使模制的底部填充材料在形成底部填充层的倒装芯片衬底上流动并形成包覆成型层; 并将所述倒装芯片基板冷却至基本上低于所述模制底部填充材料的熔融温度的第三温度。 公开了一种装置。

公开(公告)号：US08884431B2

公开(公告)日：2014-11-11

申请号：US13228768

申请日：2011-09-09

Applicant: Chih-Wei Lin ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Hsiu-Jen Lin ,  Bor-Ping Jang ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu ,  Meng-Tse Chen ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Kuei-Wei Huang ,  Wei-Hung Lin

Inventor： Chih-Wei Lin ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Hsiu-Jen Lin ,  Bor-Ping Jang ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu ,  Meng-Tse Chen ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Kuei-Wei Huang ,  Wei-Hung Lin

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/683 ,  H01L23/498 ,  H01L21/56 ,  H01L25/065 ,  H01L23/538 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H01L25/03 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/52 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68377 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06515 ,  H01L2224/09181 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/9202 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15322 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00

Abstract: Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.

Abstract translation: 公开了用于半导体器件的封装方法和结构。 在一个实施例中，封装的半导体器件包括具有第一表面和与第一表面相对的第二表面的再分配层（RDL）。 至少一个集成电路耦合到RDL的第一表面，并且多个金属凸块耦合到RDL的第二表面。 模制化合物设置在RDL的至少一个集成电路和第一表面上。