公开(公告)号：US20170012355A1

公开(公告)日：2017-01-12

申请号：US15184344

申请日：2016-06-16

Applicant: Infineon Technologies AG

Inventor： Walther Pachler ,  Gottfried Beer ,  Juergen Hoelzl ,  Juergen Schilling ,  Harald Witschnig

IPC: H01Q7/06

CPC classification number: H04B5/0081 ,  H01L21/568 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/96

Abstract: A ferrite antenna is disclosed. The ferrite antenna includes a ferrite core a first main face, a second main face opposite to the first main face, and side faces connecting the first and second main faces. A first plurality of conductor wires are disposed at the first main face of the ferrite core; a second plurality of conductor wires disposed at the second main face of the ferrite core. A first connection member is disposed at a first side face of the ferrite core, the first connection member including a first plurality of connection wires; and a second connection member is disposed at a second side face of the ferrite core, the second connection member including a second plurality of connection wires; wherein the first and second pluralities of conductor wires and the first and second plurality of connection wires are interconnected in such a way that they form an antenna coil, wherein the ferrite core is disposed in the interior space of the antenna coil.

Abstract translation: 公开了一种铁氧体天线。 铁氧体天线包括铁氧体磁芯，第一主面，与第一主面相对的第二主面，以及连接第一主面和第二主面的侧面。 第一多根导体线设置在铁氧体磁芯的第一主面上; 设置在铁氧体磁芯的第二主面上的第二多个导线。 第一连接构件设置在铁氧体磁芯的第一侧面，第一连接构件包括第一多个连接线; 并且第二连接构件设置在所述铁氧体磁芯的第二侧面，所述第二连接构件包括第二多个连接线; 其中所述第一和第二多条导线以及所述第一和第二多条连接线以这样的方式互连，使得它们形成天线线圈，其中所述铁氧体磁芯设置在所述天线线圈的内部空间中。

公开(公告)号：US09496237B2

公开(公告)日：2016-11-15

申请号：US14715778

申请日：2015-05-19

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Raimund Foerg ,  Juergen Hoegerl

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/48

CPC classification number: H01L24/14 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/0381 ,  H01L2224/039 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05562 ,  H01L2224/05564 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06132 ,  H01L2224/06133 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/06177 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/119 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13562 ,  H01L2224/13644 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/16145 ,  H01L2224/26145 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/13055 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2224/03464

Abstract: A semiconductor device includes a semiconductor chip and a plurality of electrical contact pads disposed on a main face of the semiconductor chip, wherein the electrical contact pads each include a layer stack, each layer stack having one and the same order of layers, and wherein the electrical contact pads are both solderable and bondable.

Abstract translation: 半导体器件包括半导体芯片和设置在半导体芯片的主面上的多个电接触焊盘，其中电接触焊盘各自包括层堆叠，每个层堆叠具有一层且相同的层数，并且其中 电接触焊盘都是可焊接和可焊接的。

公开(公告)号：US09337155B2

公开(公告)日：2016-05-10

申请号：US14207777

申请日：2014-03-13

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Juergen Hoegerl ,  Thilo Stolze

IPC: H01L23/31 ,  H01L25/07 ,  H01L23/00 ,  H01L23/29 ,  H01L25/00 ,  H01L29/16 ,  H01L21/56

CPC classification number: H01L23/564 ,  H01L21/561 ,  H01L21/568 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3135 ,  H01L24/48 ,  H01L25/072 ,  H01L25/50 ,  H01L29/1608 ,  H01L2224/29101 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/48491 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/85423 ,  H01L2924/00014 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A semiconductor component includes a semiconductor body having a top side and a bottom side opposite the top side. A top metallization is applied to the top side and a bottom metallization is applied to the bottom side. A moisture barrier completely seals the semiconductor body in cooperation with the top metallization and the bottom metallization.

Abstract translation: 半导体部件包括具有与顶侧相对的顶侧和底侧的半导体本体。 顶部金属化被施加到顶侧，并且底部金属化被施加到底侧。 与顶部金属化和底部金属化相配合，防潮层完全密封半导体本体。

公开(公告)号：US20160084887A1

公开(公告)日：2016-03-24

申请号：US14837048

申请日：2015-08-27

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Wolfgang Furtner

IPC: G01R15/14 ,  G01R19/00

CPC classification number: G01R15/146 ,  G01R1/203 ,  G01R19/0092 ,  G01R19/32 ,  H01L2224/11

Abstract: The electronic device for sensing a current comprises a semiconductor chip comprising a main face, an electronic circuit integrated in the semiconductor chip, a redistribution metallization layer disposed above the main face of the semiconductor chip, a current path formed in the redistribution metallization layer, the current path forming a resistor that is connected at two resistance defining end points to the electronic circuit for sensing a current flowing through the current path, and external contact elements connected with the redistribution metallization layer for feeding a current to be sensed into the current path.

Abstract translation: 用于感测电流的电子设备包括半导体芯片，其包括主面，集成在半导体芯片中的电子电路，设置在半导体芯片的主面上方的再分布金属化层，形成在再分布金属化层中的电流路径， 电流路径形成电阻器，其连接在限定端点的电阻的两个电阻处，用于感测流过电流路径的电流，以及与再分布金属化层连接的外部接触元件，用于将要感测的电流馈送到电流路径。

公开(公告)号：US09147585B2

公开(公告)日：2015-09-29

申请号：US14535591

申请日：2014-11-07

Applicant: Infineon Technologies AG

Inventor： Thomas Kilger ,  Ulrich Wachter ,  Dominic Maier ,  Gottfried Beer

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/82 ,  H01L21/56 ,  H01L23/538 ,  H01L27/04 ,  H01L49/02 ,  H01L23/00 ,  H01L21/78 ,  H01L25/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L21/82 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L25/50 ,  H01L27/04 ,  H01L28/00 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/00

Abstract: A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices.

Abstract translation: 多个半导体芯片各自包括与第一主面相对的第一主面和第二主面。 在半导体芯片的第二主面上施加第一封装层。 在第一半导体芯片的第一主面上施加电布线层。 将第二封装层施加在电布线层上。 第一封装层的厚度和第一半导体芯片的厚度减小。 可以将该结构单个化以获得多个半导体器件。

公开(公告)号：US09082644B2

公开(公告)日：2015-07-14

申请号：US13745550

申请日：2013-01-18

Applicant: Infineon Technologies AG

Inventor： Peter Ossimitz ,  Matthias von Daak ,  Gottfried Beer

IPC: H01L21/66 ,  G01R31/28

CPC classification number: H01L22/10 ,  G01R31/2884 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A method of producing and testing a chip package is described. The chip package to be produced includes a semiconductor chip containing an integrated circuit and a reinforcing structure attached to the semiconductor chip. Further, the chip package has a lower main face and an upper main face opposite to the lower main face, wherein the lower main face is at least partly formed by an exposed surface of the semiconductor chip and the upper main face is formed by a terminal surface of the reinforcing structure on which external terminal pads of the chip package are arranged. After production, the package is subjected to a package-level burn-in test.

Abstract translation: 描述了制造和测试芯片封装的方法。 要制造的芯片封装包括一个包含集成电路的半导体芯片和一个附着在半导体芯片上的加强结构。 此外，芯片封装具有与下主面相对的下主面和上主面，其中下主面至少部分地由半导体芯片的暴露表面形成，并且上主面由终端形成 所述加强结构的表面布置有所述芯片封装的外部端子焊盘。 生产后，对包装进行封装级老化测试。

公开(公告)号：US20150162318A1

公开(公告)日：2015-06-11

申请号：US14101370

申请日：2013-12-10

Applicant: Infineon Technologies AG

Inventor： Robert Allinger ,  Gottfried Beer ,  Juergen Hoegerl

IPC: H01L25/18 ,  H01L23/00 ,  H01L27/02 ,  H01L21/66

CPC classification number: H01L25/18 ,  G01R31/2884 ,  H01L22/26 ,  H01L22/34 ,  H01L24/06 ,  H01L24/09 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0248 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06132 ,  H01L2224/06136 ,  H01L2224/13147 ,  H01L2224/16148 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06596 ,  H01L2924/14 ,  H01L2924/14252 ,  H01L2924/14253 ,  H01L2924/1426 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: In various embodiments, a chip for a chip package is provided. The chip may include a substrate and an integrated circuit over the substrate. The integrated circuit may include a test circuit, for example a built-in self-test circuit, and an operation circuit, the test circuit including one or more first driver stages each having a first driver performance and the operation circuit including one or more second driver stages each having a second driver performance which is different from the first driver performance, first contacts electrically coupled with the first driver stages, and second contacts electrically coupled with the second driver stages, wherein the test circuit and the first contacts are configured to provide a test mode for testing the integrated circuit and wherein the operation circuit and the second contacts are configured to provide an operating mode of the integrated circuit being different from the test mode.

Abstract translation: 在各种实施例中，提供了用于芯片封装的芯片。 芯片可以包括衬底和衬底上的集成电路。 集成电路可以包括测试电路，例如内置的自检电路和操作电路，测试电路包括一个或多个第一驱动器级，每个具有第一驱动器性能，并且该操作电路包括一个或多个第二 驱动器级各自具有与第一驱动器性能不同的第二驱动器性能，第一触点与第一驱动级电耦合，以及与第二驱动级电耦合的第二触点，其中测试电路和第一触点被配置为提供 用于测试集成电路的测试模式，并且其中所述操作电路和所述第二触点被配置为提供与所述测试模式不同的所述集成电路的操作模式。

公开(公告)号：US20150061144A1

公开(公告)日：2015-03-05

申请号：US14476241

申请日：2014-09-03

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Irmgard Escher-Poeppel ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/07 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L21/56 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/24 ,  H01L24/33 ,  H01L24/72 ,  H01L24/82 ,  H01L24/90 ,  H01L24/96 ,  H01L24/97 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/29011 ,  H01L2224/33181 ,  H01L2224/82039 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/35 ,  H01L2924/00

Abstract: A semiconductor arrangement includes upper and lower contact plates and basic chip assemblies. Each chip assembly has a semiconductor chip having a semiconductor body with upper and lower spaced apart sides. An individual upper main electrode and an individual control electrode are arranged on the upper side. The chip assemblies have either respectively a separate lower main electrode arranged on the lower side of the semiconductor chip of the corresponding basic chip assembly, or a common lower main electrode, which for each of the chip assemblies is arranged on the lower side of the semiconductor body of that chip assembly. An electrical current between the individual upper main electrode and the individual or common lower main electrode is controllable by its control electrode. The chip assemblies are connected to one another with a material bonded connection by a dielectric embedding compound, forming a solid assembly.

Abstract translation: 半导体装置包括上和下接触板和基本芯片组件。 每个芯片组件具有半导体芯片，半导体芯片具有上部和下部间隔开的侧面的半导体本体。 单独的上主电极和单独的控制电极设置在上侧。 芯片组件分别具有布置在相应的基本芯片组件的半导体芯片的下侧上的单独的下部主电极或共同的下部主电极，其中每个芯片组件布置在半导体的下侧 该芯片组件的主体。 各个上主电极和单个或公共下主电极之间的电流可由其控制电极控制。 芯片组件通过电介质嵌入化合物的材料结合连接彼此连接，形成固体组件。

公开(公告)号：US20190221521A1

公开(公告)日：2019-07-18

申请号：US16249172

申请日：2019-01-16

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Juergen Hoegerl ,  Gottfried Beer ,  Magdalena Hoier ,  Georg Meyer-Berg

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/00 ,  H01L24/25 ,  H01L25/00

Abstract: A power semiconductor module includes a power semiconductor die attached to the first metallized side, a passive component attached to the first metallized side, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component.

公开(公告)号：US20170288176A1

公开(公告)日：2017-10-05

申请号：US15628682

申请日：2017-06-21

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Walter Hartner

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/538 ,  H01Q1/22 ,  H01Q23/00 ,  H01L23/31 ,  H01L23/66 ,  H01L25/10 ,  H01L25/16

CPC classification number: H01L24/82 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05599 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24195 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1423 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/207 ,  H01Q1/2283 ,  H01Q23/00 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.