公开(公告)号：US09780079B2

公开(公告)日：2017-10-03

申请号：US14700222

申请日：2015-04-30

Applicant: Micron Technology, Inc.

Inventor： Jian Li ,  Steven K. Groothuis

IPC: H01L23/34 ,  H01L25/18 ,  H01L25/065 ,  H01L23/367 ,  H01L25/00 ,  H01L23/055 ,  H01L23/13 ,  H01L23/00 ,  H01L21/683

CPC classification number: H01L25/18 ,  H01L21/6835 ,  H01L23/055 ,  H01L23/13 ,  H01L23/3675 ,  H01L23/3677 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05171 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/92225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15793 ,  H01L2924/16251 ,  H01L2924/16747 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Semiconductor die assemblies and methods of forming the same are described herein. As an example, a semiconductor die assembly may include a thermally conductive casing, a first face of a logic die coupled to the thermally conductive casing to form a thermal path that transfers heat away from the logic die to the thermally conductive casing, a substrate coupled to a second face of the logic die, and a die embedded at least partially in a cavity of the substrate.

公开(公告)号：US20170236589A1

公开(公告)日：2017-08-17

申请号：US15583411

申请日：2017-05-01

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Jian Li ,  Chandra Mouli

IPC: G11C16/14 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/161 ,  H01L29/08 ,  H01L29/16 ,  H01L29/20 ,  H01L29/22 ,  G11C16/04 ,  H01L27/11582

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/7926

Abstract: Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.

公开(公告)号：US09620709B2

公开(公告)日：2017-04-11

申请号：US15048746

申请日：2016-02-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Liu ,  Jian Li

IPC: G11C11/00 ,  H01L45/00 ,  G11C13/00

CPC classification number: H01L45/06 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/008 ,  G11C2213/52 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141

Abstract: Embodiments disclosed herein may relate to heating a phase change memory (PCM) cell.

公开(公告)号：US09443744B2

公开(公告)日：2016-09-13

申请号：US14330934

申请日：2014-07-14

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/56 ,  H01L25/065 ,  H01L25/16 ,  H01L25/00 ,  H01L23/04 ,  H01L21/50 ,  H01L23/36 ,  H01L23/367 ,  H01L21/48

CPC classification number: H01L25/50 ,  H01L21/4882 ,  H01L21/50 ,  H01L21/563 ,  H01L23/04 ,  H01L23/36 ,  H01L23/3675 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/167 ,  H01L2224/16145 ,  H01L2225/06568 ,  H01L2225/06589

Abstract: A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.

Abstract translation: 具有高效率热路径的半导体管芯组件。 在一个实施例中，半导体管芯组件包括封装支撑衬底，具有周边区域和堆叠区域的第一半导体管芯，以及附接到第一管芯的堆叠区域的第二半导体管芯，使得外围区域是 第二次死亡 组件还包括热传递单元，其具有附接到第一模具的周边区域的基座，通过粘合剂附接到基座的盖子以及至少由盖子限定的空腔，其中第二模具在空腔内。 组件还包括在腔中的底部填充物，其中底部填充物的圆角部分沿着基脚的一部分向上延伸一段距离，并沿基部的至少一部分向上延伸。

公开(公告)号：US20160013115A1

公开(公告)日：2016-01-14

申请号：US14330934

申请日：2014-07-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L23/34 ,  H01L21/56 ,  H01L25/16 ,  H01L25/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/4882 ,  H01L21/50 ,  H01L21/563 ,  H01L23/04 ,  H01L23/36 ,  H01L23/3675 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/167 ,  H01L2224/16145 ,  H01L2225/06568 ,  H01L2225/06589

Abstract: A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.

Abstract translation: 具有高效率热路径的半导体管芯组件。 在一个实施例中，半导体管芯组件包括封装支撑衬底，具有周边区域和堆叠区域的第一半导体管芯，以及附接到第一管芯的堆叠区域的第二半导体管芯，使得外围区域是 第二次死亡 组件还包括热传递单元，其具有附接到第一模具的周边区域的基座，通过粘合剂附接到基座的盖子以及至少由盖子限定的空腔，其中第二模具在空腔内。 组件还包括在腔中的底部填充物，其中底部填充物的圆角部分沿着基脚的一部分向上延伸一段距离，并沿基部的至少一部分向上延伸。

公开(公告)号：US09184105B2

公开(公告)日：2015-11-10

申请号：US14334870

申请日：2014-07-18

Applicant: Micron Technology, Inc.

Inventor： Steven Groothuis ,  Jian Li ,  Shijian Luo

IPC: H01L23/02 ,  H01L23/22 ,  H01L21/00 ,  H01L23/34 ,  H01L23/367 ,  H01L23/31 ,  H01L25/065 ,  H01L23/433 ,  H01L25/18

CPC classification number: H01L23/367 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3185 ,  H01L23/34 ,  H01L23/433 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: Semiconductor devices may include a first semiconductor die comprising a heat-generating region located at a periphery thereof. A second semiconductor die is attached to the first semiconductor die. At least a portion of the heat-generating region is located laterally outside a footprint of the second semiconductor die. A thermally insulating material is located on a side surface of the second semiconductor die. Methods of forming semiconductor devices may involve attaching a second semiconductor die to a first semiconductor die. The first semiconductor die includes a heat-generating region at a periphery thereof. At least a portion of the heat-generating region is located laterally outside a footprint of the second semiconductor die. A thermally insulating material is located on a side surface of the second semiconductor die.

Abstract translation: 半导体器件可以包括第一半导体管芯，其包括位于其周边的发热区域。 第二半导体管芯附接到第一半导体管芯。 发热区域的至少一部分位于第二半导体管芯的覆盖区的横向外侧。 绝热材料位于第二半导体管芯的侧表面上。 形成半导体器件的方法可以包括将第二半导体管芯附接到第一半导体管芯。 第一半导体管芯包括在其周边的发热区域。 发热区域的至少一部分位于第二半导体管芯的覆盖区的横向外侧。 绝热材料位于第二半导体管芯的侧表面上。

公开(公告)号：US11889695B2

公开(公告)日：2024-01-30

申请号：US17504313

申请日：2021-10-18

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Justin B. Dorhout ,  Indra V. Chary ,  Jun Fang ,  Matthew Park ,  Zhiqiang Xie ,  Scott D. Stull ,  Daniel Osterberg ,  Jason Reece ,  Jian Li

IPC: H01L27/11582 ,  H10B43/27 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L21/02 ,  H01L29/10 ,  H01L23/522 ,  H10B41/27 ,  H10B43/50 ,  H10B41/35 ,  H10B43/10

CPC classification number: H10B43/27 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/5226 ,  H01L29/1037 ,  H10B41/27 ,  H10B41/35 ,  H10B43/50 ,  H10B43/10

Abstract: A device comprises an array of elevationally-extending transistors and a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array. The circuit structure comprises a stair step structure comprising vertically-alternating tiers comprising conductive steps that are at least partially elevationally separated from one another by insulative material. Operative conductive vias individually extend elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and individually electrically couple to an electronic component below the vertically-alternating tiers. Dummy structures individually extend elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers. Methods are also disclosed.

公开(公告)号：US11658132B2

公开(公告)日：2023-05-23

申请号：US17559321

申请日：2021-12-22

Applicant: Micron Technology, Inc.

Inventor： Rohit Kothari ,  Lifang Xu ,  Jian Li

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11529 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

Abstract: Some embodiments include an integrated assembly having a semiconductor die with memory array regions and one or more regions peripheral to the memory array regions. A stack of alternating insulative and conductive levels extends across the memory array regions and passes into at least one of the peripheral regions. The stack generates bending stresses on the die. At least one stress-moderating region extends through the stack and is configured to alleviate the bending stresses.

公开(公告)号：US11563022B2

公开(公告)日：2023-01-24

申请号：US16550252

申请日：2019-08-25

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Indra V. Chary ,  Justin B. Dorhout ,  Jian Li ,  Haitao Liu ,  Paolo Tessariol

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/1157

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The operative channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. An elevationally-extending wall is in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks and that completely encircles an island that is laterally-between immediately-laterally-adjacent of the memory blocks in the memory plane. Other embodiments, including method are disclosed.

公开(公告)号：US20220238548A1

公开(公告)日：2022-07-28

申请号：US17158888

申请日：2021-01-26

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Litao Yang ,  Albert Fayrushin ,  Naveen Kaushik ,  Jian Li ,  Collin Howder

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative and conductive structures arranged in tiers. At least one pillar, comprising a channel material, extends through the stack structure. A source region, below the stack structure, comprises a doped material with vertical extensions that protrude to an interface with the channel material at an elevation proximate at least one source-side GIDL region. Slit structures extend through the stack structure to divide the structure into blocks of pillar arrays. A series of spaced, discrete pedestal structures are included along a base of the slit structures. Forming the microelectronic device structure may include forming a lateral opening through cell materials of the pillar, vertically recessing the channel material, and laterally recessing other material(s) of the pillar before forming the doped material in the broadened recesses. Additional microelectronic devices, related methods, and electronic systems are also disclosed.