公开(公告)号：US07982135B2

公开(公告)日：2011-07-19

申请号：US11927144

申请日：2007-10-29

Applicant: Michimasa Takahashi ,  Masakazu Aoyama

Inventor： Michimasa Takahashi ,  Masakazu Aoyama

IPC: H05K1/00

CPC classification number: H05K3/4691 ,  H05K1/0218 ,  H05K3/0035 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4664 ,  H05K2201/0187 ,  H05K2201/0715 ,  H05K2201/09127 ,  H05K2201/09509 ,  H05K2201/096 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A flex-rigid wiring board includes a flexible board including a flexible substrate and a conductor pattern formed over the flexible substrate, a non-flexible substrate disposed adjacent to the flexible board, an insulating layer including an inorganic material and covering the flexible board and the non-flexible substrate, the insulating layer exposing at least one portion of the flexible board, a conductor pattern formed on the insulating layer, and a plating layer connecting the conductor pattern of the flexible board and the conductor pattern on the insulating layer.

Abstract translation: 弹性刚性布线板包括柔性基板，该柔性基板包括柔性基板和形成在柔性基板上的导体图案，邻近柔性基板设置的非柔性基板，包括无机材料并覆盖柔性基板的绝缘层和 非柔性基板，绝缘层暴露柔性板的至少一部分，形成在绝缘层上的导体图案，以及将柔性基板的导体图案与导体图案连接在绝缘层上的镀层。

公开(公告)号：US07973248B2

公开(公告)日：2011-07-05

申请号：US12219381

申请日：2008-07-21

Applicant: Jee-Soo Mok ,  Chang-Sup Ryu ,  Eung-Suek Lee ,  Youn-Soo Seo ,  Hee-Bum Shin ,  Yoong Oh ,  Byung-Bae Seo ,  Tae-Kyoung Kim ,  Dong-Jin Park

Inventor： Jee-Soo Mok ,  Chang-Sup Ryu ,  Eung-Suek Lee ,  Youn-Soo Seo ,  Hee-Bum Shin ,  Yoong Oh ,  Byung-Bae Seo ,  Tae-Kyoung Kim ,  Dong-Jin Park

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K3/462 ,  H01R12/523 ,  H05K3/4069 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/0353 ,  Y10T29/49155

Abstract: A printed circuit board using paste bumps and manufacturing method thereof are disclosed. The method of manufacturing a printed circuit board using paste bumps, includes: (a) perforating a core board to form at least one via hole, (b) filling the at least one via hole by fill-plating and forming a circuit pattern on at least one surface of the core board, (c) stacking a paste bump board on at least one surface of the core board, and (d) forming an outer layer circuit on a surface of the paste bump board, a structurally stable all-layer IVH structure can be implemented due to increased strength in the BVH's of the plated core boards, the manufacture time can be reduced due to parallel processes and collective stacking, implementing micro circuits can be made easy due to the copper foils of the paste bump boards stacked on the outermost layers, the manufacture costs can be reduced as certain plating and drilling processes may be omitted, the interlayer connection area is increased between circuit patterns for improved connection reliability, and dimple coverage can be obtained.

Abstract translation: 公开了一种使用糊状凸块的印刷电路板及其制造方法。 使用糊状凸块制造印刷电路板的方法包括：（a）穿孔芯板以形成至少一个通孔，（b）通过填充电镀填充至少一个通孔并在其上形成电路图案 芯板的至少一个表面，（c）在芯板的至少一个表面上堆叠焊料凸块，以及（d）在焊料凸块的表面上形成外层电路，结构稳定的全层 由于镀层芯板的BVH的强度增加，可以实现IVH结构，由于并行处理和集体堆叠，制造时间可以减少，由于粘贴凸块的铜箔堆叠而实现微电路变得容易 在最外层，可以减少制造成本，因为可以省略某些电镀和钻孔工艺，在电路图案之间增加层间连接面积以提高连接可靠性，并且可以获得凹坑覆盖 d。

公开(公告)号：US20110155428A1

公开(公告)日：2011-06-30

申请号：US12785725

申请日：2010-05-24

Applicant: Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen

Inventor： Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen

IPC: H05K1/02 ,  H05K1/09 ,  B05D3/06 ,  B05D3/10 ,  H05K3/00

CPC classification number: H05K3/465 ,  C23C18/1612 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/1689 ,  H05K1/0265 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/045 ,  H05K3/107 ,  H05K2201/0391 ,  H05K2201/09509 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A circuit board includes a circuit substrate, a dielectric layer, and a patterned circuit structure. The dielectric layer covers a first surface and at least a first circuit of the circuit substrate. The dielectric layer has a second surface, at least a blind via extending from the second surface to the first circuit, a first intaglio pattern, and a second intaglio pattern. The patterned circuit structure includes at least a second circuit and a plurality of third circuits. The second circuit is disposed in the first intaglio pattern. The third circuits are disposed in the second intaglio pattern and the blind via. Each third circuit has a first conductive layer, a second conductive layer, and a barrier layer. The first conductive layer is located between the barrier layer and the second intaglio pattern and between the barrier layer and the blind via. The second conductive layer covers the barrier layer.

Abstract translation: 电路板包括电路基板，电介质层和图案化电路结构。 电介质层覆盖电路基板的第一表面和至少第一电路。 电介质层具有第二表面，至少从第二表面延伸到第一电路的盲孔，第一凹版图案和第二凹版图案。 图案化电路结构至少包括第二电路和多个第三电路。 第二电路设置在第一凹版图案中。 第三电路设置在第二凹版图案和盲孔中。 每个第三电路具有第一导电层，第二导电层和阻挡层。 第一导电层位于阻挡层和第二凹版图案之间以及阻挡层和盲孔之间。 第二导电层覆盖阻挡层。

公开(公告)号：US20110154657A1

公开(公告)日：2011-06-30

申请号：US12725641

申请日：2010-03-17

Applicant: Chih-Hong Chuang ,  Tzu-Wei Huang

Inventor： Chih-Hong Chuang ,  Tzu-Wei Huang

IPC: H05K3/00

CPC classification number: H05K3/0097 ,  H05K3/427 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2203/1536 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49169 ,  Y10T29/49176

Abstract: A manufacturing method of package carrier is provided. A first copper foil layer, a second copper foil layer on the first foil layer, a third copper foil layer and a fourth foil layer on the third foil layer are provided. The second copper foil layer is partially bonded the fourth copper foil layer by an adhesive gel so as to form a substrate of which the peripheral region is glued and the effective region is not glued. Therefore, the thinner substrate can be used in the following steps, such as patterning process or plating process. In addition, the substrate can be extended be the package carrier structure with odd-numbered layer or even-numbered layer.

Abstract translation: 提供一种封装载体的制造方法。 提供第一铜箔层，第一箔层上的第二铜箔层，第三箔层上的第三铜箔层和第四箔层。 第二铜箔层通过粘合剂凝胶部分地接合第四铜箔层，以形成周边区域被胶合并且有效区域不胶合的基板。 因此，较薄的基板可以在以下步骤中使用，例如图案化工艺或电镀工艺。 此外，衬底可以扩展为具有奇数层或偶数层的封装载体结构。

公开(公告)号：US07969745B2

公开(公告)日：2011-06-28

申请号：US11970112

申请日：2008-01-07

Applicant: Shih-Ping Hsu ,  Kan-Jung Chia

Inventor： Shih-Ping Hsu ,  Kan-Jung Chia

IPC: H05K1/18 ,  H05K1/03

CPC classification number: H05K1/185 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/73267 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/15787 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/053 ,  H05K1/162 ,  H05K3/4608 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/10674 ,  H01L2924/00

Abstract: The present invention provides a circuit board having electronic components integrated therein, including a carrier board having an metallic oxide layer formed on each two surfaces of a metal layer, and having at least one through cavity; at least a semiconductor chip hold in the opening; at least a capacitor disposed on one surface of the carrier board, wherein the surface with the capacitor disposed thereon is at the same side with the active surface of the semiconductor chip. The capacitor is constituted of a first electrode plate disposed on partial surface of one side of the carrier board, a high dielectric material layer disposed on the surface of the first electrode plate, and a second electrode plate, paralleling and corresponding to the first electrode plate, disposed on the surface of the high dielectric material. The metal layer and the oxidation layer of the carrier board can enhance rigidity as well as tenacity and also integrate semiconductor chips and capacitors in the circuit board structure.

Abstract translation: 本发明提供了一种集成有电子部件的电路板，包括：载体板，其具有在金属层的每两个表面上形成的金属氧化物层，并具有至少一个通孔; 至少一个半导体芯片保持在开口中; 至少设置在所述载板的一个表面上的电容器，其中设置有所述电容器的所述表面与所述半导体芯片的有源表面处于同一侧。 电容器由设置在载板的一侧的部分表面上的第一电极板，设置在第一电极板的表面上的高介电材料层和与第一电极板相对应的第二电极板 ，设置在高电介质材料的表面上。 载体板的金属层和氧化层可以提高刚性和强度，并且还将半导体芯片和电容器集成在电路板结构中。

公开(公告)号：US20110147068A1

公开(公告)日：2011-06-23

申请号：US12641381

申请日：2009-12-18

Applicant: Joseph J. Cahill ,  Anand Haridass ,  Roger D. Weekly

Inventor： Joseph J. Cahill ,  Anand Haridass ,  Roger D. Weekly

IPC: H05K1/11 ,  G06F17/50

CPC classification number: H05K1/0251 ,  G06F17/5077 ,  H05K1/162 ,  H05K2201/09509 ,  H05K2201/09536

Abstract: An apparatus is provided that comprises a plurality of signaling planes providing signal pathways and at least one internal reference plane providing either a voltage or a ground connection. The at least one internal reference plane are provided between at least two of the signaling planes. The apparatus further comprises a signal blind/buried via coupling a signal pathway of a first one of the at least two signaling planes with a signal pathway of a second one of the at least two signaling planes. The blind/buried via runs through the at least one internal reference plane. The apparatus also comprises at least one first conductive feature in the first one of the at least two signaling planes. The at least one first conductive feature is in close proximity to the signal blind/buried via and increases the capacitive coupling of currents in the reference planes of the apparatus.

Abstract translation: 提供了一种装置，其包括提供信号路径的多个信令平面和提供电压或接地连接的至少一个内部参考平面。 所述至少一个内部参考平面设置在至少两个信令平面之间。 该装置还包括通过将至少两个信令平面中的第一个信号平面的第一信号平面的信号路径与至少两个信令平面中的第二信号平面的信号路径耦合而进行信号盲/掩蔽。 盲/埋通孔穿过至少一个内部参考平面。 该装置还包括至少两个信令平面中的第一个中的至少一个第一导电特征。 至少一个第一导电特征与信号盲/掩埋通孔紧密接近，并且增加了装置参考平面中电流的电容耦合。

公开(公告)号：US07948766B2

公开(公告)日：2011-05-24

申请号：US12504251

申请日：2009-07-16

Applicant: Gregory M. Jandzio ,  Anders P. Pedersen ,  Gary A. Rief ,  Walter M. Whybrew

Inventor： Gregory M. Jandzio ,  Anders P. Pedersen ,  Gary A. Rief ,  Walter M. Whybrew

IPC: H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H05K1/0243 ,  H01Q3/26 ,  H01Q21/0006 ,  H01Q21/0037 ,  H05K3/429 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/10553 ,  H05K2203/049 ,  Y10T29/49165

Abstract: A method is for making a structural printed wiring board panel that includes a multilayer printed wiring board having opposing, outer faces and interlayer interconnects that route RF, power and control signals. Connection areas are formed in or on at least on one face for connecting the interlayer interconnects and any electrical components. A metallic face sheet is secured onto at least one outer face, adding structural rigidity to the multilayer printed wiring board. A metallic face sheet can have apertures positioned to allow access to connection areas. RF components can be carried by a face sheet and operatively connected to connection areas. Antenna elements can be positioned on the same or an opposing face sheet and operatively connected to RF components to form a phased array printed wiring board (PWB) panel.

Abstract translation: 一种用于制造结构印刷线路板面板的方法，该结构印刷线路板面板包括具有相对的外表面和层间互连的多层印刷线路板，其路由RF，功率和控制信号。 连接区域形成在至少一个面上或之上，用于连接层间互连和任何电气部件。 金属面板固定在至少一个外表面上，为多层印刷线路板增加结构刚性。 金属面板可以具有定位成允许接近连接区域的孔。 RF部件可以由面板承载并且可操作地连接到连接区域。 天线元件可以定位在相同或相对的面板上并且可操作地连接到RF部件以形成相控阵列印刷线路板（PWB）面板。

公开(公告)号：US20110108427A1

公开(公告)日：2011-05-12

申请号：US13008849

申请日：2011-01-18

Applicant: Charan Gurumurthy ,  Sanka Ganesan ,  Chandrashekar Ramaswamy ,  Mark Hlad

Inventor： Charan Gurumurthy ,  Sanka Ganesan ,  Chandrashekar Ramaswamy ,  Mark Hlad

IPC: C25D5/02

CPC classification number: H01L23/48 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/113 ,  H05K3/00 ,  H05K3/108 ,  H05K3/222 ,  H05K3/426 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/10189 ,  H05K2201/10356 ,  H05K2201/1053 ,  H05K2201/10734 ,  H05K2203/167 ,  Y10T29/49124 ,  H01L2224/0401

Abstract: An assembly of substrate packages interconnected with flex cables and a method of fabrication of the substrate package. The assembly allows input/output (I/O) signals to be speedily transmitted between substrate packages via flex cable and without being routed through the motherboard. Embodiments relate to a substrate package providing separable inter-package flex cable connection. Hermetically-sealed guiding through holes are provided on the substrate package as a mechanical alignment feature to guide connection between flex cables and high speed I/O contact pads on the substrate package. Embodiments of the method of fabrication relate to simultaneously forming hermetically-sealed guiding through holes and I/O contact pads.

Abstract translation: 与柔性电缆互连的衬底封装的组件和衬底封装的制造方法。 该组件允许通过柔性电缆快速地在衬底封装之间传输输入/输出（I / O）信号，而不通过主板。 实施例涉及提供可分离的包装间柔性电缆连接的衬底封装。 在基板封装上提供密封导向孔，作为机械对准特征，以引导柔性电缆与基板封装上的高速I / O接触焊盘之间的连接。 制造方法的实施例涉及同时形成密封的引导通孔和I / O接触垫。

公开(公告)号：US20110088930A1

公开(公告)日：2011-04-21

申请号：US12651191

申请日：2009-12-31

Applicant: Jae-Seok LEE

Inventor： Jae-Seok LEE

IPC: H05K1/02 ,  B32B37/00

CPC classification number: H05K3/10 ,  H05K3/0097 ,  H05K3/061 ,  H05K3/205 ,  H05K3/22 ,  H05K3/28 ,  H05K3/421 ,  H05K3/428 ,  H05K3/4658 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2203/054 ,  H05K2203/0571 ,  H05K2203/0574

Abstract: A printed circuit board and a manufacturing method of the same are disclosed. The method includes: preparing a carrier including a primer resin layer formed thereon; forming a circuit pattern on the primer resin layer; stacking the carrier onto an insulating layer such that the circuit pattern is buried in the insulating layer; removing the carrier; forming a via hole in the insulating layer on which the primer resin layer is stacked; and forming a conductive via in the via hole. The conductive via is formed by forming a plating layer in the via hole and on the primer resin layer and removing a portion of the plating layer formed over the primer resin layer.

Abstract translation: 公开了一种印刷电路板及其制造方法。 该方法包括：制备其上形成有底漆树脂层的载体; 在底漆树脂层上形成电路图案; 将载体堆叠在绝缘层上，使得电路图案埋在绝缘层中; 移除载体; 在其上层叠有底漆树脂层的绝缘层中形成通孔; 以及在所述通孔中形成导电通孔。 导电孔通过在通孔中和底漆树脂层上形成镀层而除去在底漆树脂层上形成的镀层的一部分而形成。

公开(公告)号：US07911803B2

公开(公告)日：2011-03-22

申请号：US11872870

申请日：2007-10-16

Applicant: Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

Inventor： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

IPC: H05K7/10

CPC classification number: H01L24/10 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05558 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/0265 ,  H05K1/111 ,  H05K1/112 ,  H05K2201/0769 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/0979 ,  Y02P70/611 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49179 ,  H01L2924/00

Abstract: An electrical structure and method of forming. The electrical structure comprises an interconnect structure and a substrate. The substrate comprises an electrically conductive pad and a plurality of wire traces electrically connected to the electrically conductive pad. The electrically conductive pad is electrically and mechanically connected to the interconnect structure. The plurality of wire traces comprises a first wire trace, a second wire trace, a third wire trace, and a fourth wire trace. The first wire trace and second wire trace are each electrically connected to a first side of the electrically conductive pad. The third wire trace is electrically connected to a second side of the electrically conductive pad. The fourth wire trace is electrically connected to a third side of said first electrically conductive pad. The plurality of wire traces are configured to distribute a current.

Abstract translation: 一种电气结构和成型方法。 电结构包括互连结构和衬底。 衬底包括导电焊盘和电连接到导电焊盘的多个导线迹线。 导电焊盘电连接和机械连接到互连结构。 多条导线包括第一线迹线，第二线迹线，第三线迹线和第四线迹线。 第一线迹和第二线迹均电连接到导电垫的第一侧。 第三线迹电连接到导电垫的第二侧。 第四线迹电连接到所述第一导电焊盘的第三侧。 多个导线配置成分布电流。