公开(公告)号：US20070194435A1

公开(公告)日：2007-08-23

申请号：US11618159

申请日：2006-12-29

申请人： Yoshihiko SHIMANUKI

发明人： Yoshihiko SHIMANUKI

IPC分类号： H01L23/12

CPC分类号： H01L23/49822 ,  H01L21/561 ,  H01L23/145 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2223/54486 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H05K1/0366 ,  H05K3/0052 ,  H05K2201/029 ,  H05K2203/0228 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： Peeling of the core material in the wiring substrate of a semiconductor device is suppressed.The multi-chip substrate is divided so that the foldout direction of fiber and the dividing direction of a substrate in each of first core material of two sheets of a multi-chip substrate may accomplish an acute angle, and fiber is exposed to the end face formed of this division. When the foldout direction of each fiber of the first core material of two sheets and the extending direction of the end face accomplish an acute angle, fiber woven into first core material can be made fine. Exposure of the portion of resin comparatively weak to stress can be lessened. As a result, peeling of resin in a cutting plane can be suppressed. Since the foldout direction and the dividing direction of fiber are an acute angle, progress of peeling can be suppressed.

摘要翻译： 抑制半导体器件的布线基板中的芯材的剥离。 多芯片基板被分割成使得两片多芯片基板的每个第一芯材中的纤维的折叠方向和基板的分割方向可以实现锐角，并且光纤暴露于端面 由此组成。 当两片的第一芯材的每个纤维的折叠方向和端面的延伸方向达到锐角时，可以使编织成第一芯材的纤维细。 可以减轻树脂部分相对弱的应力暴露。 结果，可以抑制切割平面中的树脂的剥离。 由于折叠方向和纤维的分割方向是锐角，因此可以抑制剥离的进行。

公开(公告)号：US20070158392A1

公开(公告)日：2007-07-12

申请号：US11606027

申请日：2006-11-30

申请人： Yoshihiko Shimanuki

发明人： Yoshihiko Shimanuki

IPC分类号： A47J36/02

CPC分类号： H01L24/85 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/97 ,  H01L25/0657 ,  H01L2221/68331 ,  H01L2223/5442 ,  H01L2223/54486 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48479 ,  H01L2224/48499 ,  H01L2224/48599 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49429 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/78302 ,  H01L2224/85001 ,  H01L2224/85009 ,  H01L2224/85051 ,  H01L2224/8518 ,  H01L2224/85186 ,  H01L2224/85205 ,  H01L2224/85986 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/01079 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/01013 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01006 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Wire connection failure in semiconductor device is prevented.A semiconductor device has a package substrate having, at the periphery of the main surface thereof, a plurality of bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the plurality of wires, and a plurality of solder bumps disposed on the back surface of the package substrate. The top of the loop of each of the wires is disposed outside the wire connecting portion so that the wire length wire can be increased in the connection between the bonding leads and the pads of the semiconductor chip. As a result, the wires have a stable loop shape and a wire connection failure can be prevented.

摘要翻译： 防止半导体器件中的导线连接故障。 半导体器件具有封装基板，在其主表面的周围设有多个排列成一排的接合引线，安装在封装基板的主表面上的接合引线列内的半导体芯片，导线 用于连接半导体芯片的焊盘和基板的接合引线，用于树脂密封半导体芯片和多个引线的密封体以及设置在封装基板的背面上的多个焊料凸块。 每个电线的环的顶部设置在电线连接部分的外侧，使得可以在接合引线和半导体芯片的焊盘之间的连接中增加导线长度线。 结果，电线具有稳定的环形，并且可以防止电线连接故障。

公开(公告)号：US06930380B2

公开(公告)日：2005-08-16

申请号：US10860072

申请日：2004-06-04

申请人： Yoshihiko Shimanuki ,  Hisashi Hasunuma

发明人： Yoshihiko Shimanuki ,  Hisashi Hasunuma

IPC分类号： H01L21/60 ,  H01L23/12 ,  H01L23/485 ,  H01L23/495 ,  H01L23/528 ,  H01L23/538 ,  H01L29/73

CPC分类号： H01L24/85 ,  H01L23/4952 ,  H01L23/5286 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48624 ,  H01L2224/48699 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/73265 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85951 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/78 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor chip, a plurality of bonding pads which are formed on a main surface of the semiconductor chip and include first power source bonding pads, second power source bonding pads and a plurality of signal bonding pads, a plurality of leads which are arranged around the semiconductor chip and include first power source leads and a plurality of signal leads, a plurality of bonding wires which include first bonding wires for connecting the first power source bonding pads with the first power source leads, second bonding wires for connecting the first bonding pads with second bonding pads and third bonding wires for connecting the plurality of signal bonding pads with the plurality of signal leads, and a sealing body which seals the semiconductor chip, the plurality of bonding wires and some of the plurality of leads.

摘要翻译： 半导体器件包括半导体芯片，形成在半导体芯片的主表面上的多个接合焊盘，包括第一电源接合焊盘，第二电源焊盘和多个信号焊盘，多个引线， 布置在半导体芯片的周围，并且包括第一电源引线和多个信号引线，多个接合线，包括用于将第一电源接合焊盘与第一电源引线连接的第一接合线，用于连接 具有第二接合焊盘的第一接合焊盘和用于将多个信号接合焊盘与多个信号引线连接的第三接合线，以及密封半导体芯片，多个接合线和多个引线中的一些引线的密封体。

公开(公告)号：US06927096B2

公开(公告)日：2005-08-09

申请号：US10700577

申请日：2003-11-05

申请人： Yoshihiko Shimanuki

发明人： Yoshihiko Shimanuki

IPC分类号： H01L23/12 ,  H01L21/48 ,  H01L21/60 ,  H01L23/31 ,  H01L23/495 ,  H01L23/50 ,  H01L25/04 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L21/44

CPC分类号： H01L23/49541 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2924/20752 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method of producing a thin, non-lead type semiconductor device superior in packaging performance is to be provided. A recess and grooves are formed on a main surface of a conductive substrate in accordance with predetermined patterns to define plural compartments surrounded with the recess and grooves, and plural product-forming portions are formed each by one or plural recesses and plural compartments. Thereafter, a back surface of a semiconductor element is fixed onto a depressed bottom of each of the product-forming portions through an adhesive, then electrodes formed on the semiconductor element and the compartments are connected with each other through conductive wires, an insulating resin is formed on the main surface of the substrate so as to cover the semiconductor element and the wires, then a back surface of the substrate is removed a predetermined thickness, thereby allowing the compartments to be electrically isolated each independently and allowing the adhesive to be exposed, a plating film is formed on surfaces of the compartments exposed to a surface of the resin layer, and the resin layer is cut along boundary portions of the product-forming portions to fabricate plural, thin, non-lead type semiconductor devices in each of which the back surface of the semiconductor element is lower than the main surfaces of the compartments.

摘要翻译： 提供一种制造具有优异的包装性能的薄型非引线型半导体器件的方法。 根据预定图案，在导电基板的主表面上形成凹槽和槽，以限定由凹槽和凹槽包围的多个隔室，并且多个产品形成部分由一个或多个凹部和多个隔室形成。 此后，通过粘合剂将半导体元件的背面固定在每个产品形成部分的凹陷的底部，然后通过导线将形成在半导体元件和隔间上的电极彼此连接，绝缘树脂为 形成在基板的主表面上以覆盖半导体元件和导线，然后将基板的后表面去除预定厚度，从而允许隔室独立地电隔离并允许粘合剂暴露， 在暴露于树脂层的表面的隔室的表面上形成镀膜，沿着产品形成部分的边界部分切割树脂层，以制造多个薄的非引线型半导体器件，每个半导体器件 半导体元件的背面比隔室的主表面低。

公开(公告)号：US08115298B2

公开(公告)日：2012-02-14

申请号：US12897221

申请日：2010-10-04

申请人： Yoshihiko Shimanuki

发明人： Yoshihiko Shimanuki

IPC分类号： H01L23/495

CPC分类号： H01L23/49503 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/743 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/29 ,  H01L2224/29007 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32014 ,  H01L2224/32055 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/743 ,  H01L2224/78301 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/0103 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2924/00012

摘要： A semiconductor device is disclosed which includes a tab (5) for use in supporting a semiconductor chip (8), a seal section (12) as formed by sealing the semiconductor chip (8) with a resin material, more than one tab suspension lead (4) for support of the tab (5), a plurality of electrical leads (2) which have a to-be-connected portion as exposed to outer periphery on the back surface of the seal section (12) and a thickness reduced portion as formed to be thinner than said to-be-connected portion and which are provided with an inner groove (2e) and outer groove (2f) in a wire bonding surface (2d) as disposed within the seal section (12) of said to-be-connected portion, and wires (10) for electrical connection between the leads (2) and pads (7) of the semiconductor chip (8), wherein said thickness reduced portion of the leads (2) is covered by or coated with a sealing resin material while causing the wires (10) to be contacted with said to-be-connected portion at specified part lying midway between the outer groove (2f) and inner groove (2e) to thereby permit said thickness reduced portion of leads (2) and the outer groove (2f) plus the inner groove (2e) to prevent occurrence of any accidental lead drop-down detachment.

摘要翻译： 公开了一种半导体器件，其包括用于支撑半导体芯片（8）的突片（5），通过用树脂材料密封半导体芯片（8）形成的密封部分（12），多于一个突片悬挂引线 （4），用于支撑突片（5），多个电引线（2），其具有暴露于密封部分（12）的背面上的外周的待连接部分和厚度减小部分 形成为比所述待连接部分薄，并且在设置在所述待连接部分的密封部分（12）内的引线接合表面（2d）中设置有内槽（2e）和外槽（2f） 以及用于在所述引线（2）和所述半导体芯片（8）的焊盘（7）之间电连接的导线（10），其中所述引线（2）的所述厚度减小部分被覆盖或涂覆 密封树脂材料，同时使导线（10）在指定部分放置时与所述待连接部分接触 在外槽（2f）和内槽（2e）之间的中间，从而允许引线（2）和外槽（2f）加上内槽（2e）的所述厚度减小部分，以防止任何意外的铅下降 分离。

公开(公告)号：US20110089548A1

公开(公告)日：2011-04-21

申请号：US12953499

申请日：2010-11-24

申请人： YOSHIHIKO SHIMANUKI ,  Yoshihiro Suzuki ,  Koji Tsuchiya

发明人： YOSHIHIKO SHIMANUKI ,  Yoshihiro Suzuki ,  Koji Tsuchiya

IPC分类号： H01L23/495

CPC分类号： H01L24/97 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/351 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： There are constituted by a tab (1b) on which a semiconductor chip (2) is mounted, a sealing portion (3) formed by resin-sealing the semiconductor chip (2), a plurality of leads (1a) each having a mounted surface (1d) exposed to a peripheral portion of a rear surface (3a) of the sealing portion (3) and a sealing-portion forming surface (1g) disposed on an opposite side thereto, and a wire (4) for connecting a pad (2a) of the semiconductor chip (2) and a lead (1a), wherein the length (M) between inner ends (1h) of the sealing-portion forming surfaces (1g) of the leads (1a) disposed so as to oppose to each other is formed to be larger than the length (L) between inner ends (1h) of the mounted surfaces (1d). Thereby, a chip mounting region surrounded by the inner end (1h) of the sealing-portion forming surface (1g) of each lead (1a) can be expanded and the size of the mountable chip is increased.

摘要翻译： 由安装有半导体芯片（2）的突片（1b），通过树脂密封半导体芯片（2）形成的密封部分（3），多个引线（1a），其具有安装表面 （1d）暴露于密封部分（3）的后表面（3a）的周边部分和设置在其相对侧上的密封部分形成表面（1g）和用于连接焊盘（4）的焊丝（4） 2a）和引线（1a）之间的长度（M），其中引线（1a）的密封部分形成表面（1g）的内端（1h）之间的长度（M）设置为与 彼此形成为大于安装面（1d）的内端（1h）之间的长度（L）。 由此，可以扩大由每个引线（1a）的密封部形成面（1g）的内端（1h）包围的芯片安装区域，并且可安装芯片的尺寸增大。

公开(公告)号：US07843049B2

公开(公告)日：2010-11-30

申请号：US12408890

申请日：2009-03-23

申请人： Yoshihiko Shimanuki ,  Yoshihiro Suzuki ,  Koji Tsuchiya

发明人： Yoshihiko Shimanuki ,  Yoshihiro Suzuki ,  Koji Tsuchiya

IPC分类号： H01L23/02

CPC分类号： H01L24/97 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/351 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： There are constituted by a tab (1b) on which a semiconductor chip (2) is mounted, a sealing portion (3) formed by resin-sealing the semiconductor chip (2), a plurality of leads (1a) each having a mounted surface (1d) exposed to a peripheral portion of a rear surface (3a) of the sealing portion (3) and a sealing-portion forming surface (1g) disposed on an opposite side thereto, and a wire (4) for connecting a pad (2a) of the semiconductor chip (2) and a lead (1a), wherein the length (M) between inner ends (1h) of the sealing-portion forming surfaces (1g) of the leads (1a) disposed so as to oppose to each other is formed to be larger than the length (L) between inner ends (1h) of the mounted surfaces (1d). Thereby, a chip mounting region surrounded by the inner end (1h) of the sealing-portion forming surface (1g) of each lead (1a) can be expanded and the size of the mountable chip is increased.

摘要翻译： 由安装有半导体芯片（2）的突片（1b），通过树脂密封半导体芯片（2）形成的密封部分（3），多个引线（1a），其具有安装表面 （1d）暴露于密封部分（3）的后表面（3a）的周边部分和设置在其相对侧上的密封部分形成表面（1g）和用于连接焊盘（4）的焊丝（4） 2a）和引线（1a）之间的长度（M），其中引线（1a）的密封部分形成表面（1g）的内端（1h）之间的长度（M）设置为与 彼此形成为大于安装面（1d）的内端（1h）之间的长度（L）。 由此，可以扩大由每个引线（1a）的密封部形成面（1g）的内端（1h）包围的芯片安装区域，并且可安装芯片的尺寸增大。

公开(公告)号：US07576422B2

公开(公告)日：2009-08-18

申请号：US12147905

申请日：2008-06-27

申请人： Yoshihiko Shimanuki

发明人： Yoshihiko Shimanuki

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/4554

摘要： The present invention enhances the reliability of a semiconductor device. The semiconductor device includes a package substrate having a dry resist film which covers some conductive portions out of a plurality of conductive portions formed on a main surface and a back surface and is formed of a film, a semiconductor chip which is mounted over the package substrate, conductive wires which electrically connect the semiconductor chip with the package substrate, a die-bonding film which is arranged between the main surface of the package substrate and the semiconductor chip, a plurality of solder bumps which are formed on the back surface of the package substrate, and a sealing body which is made of resin. By forming the dry resist film made of a film on the main surface and the back surface of the package substrate, it is possible to suppress the warping of the package substrate and hence, the occurrence of package cracks at the time of reflow mounting can be prevented thus enhancing the reliability of the semiconductor device.

摘要翻译： 本发明提高了半导体器件的可靠性。 该半导体器件包括：具有干膜的封装基板，该干电阻膜覆盖形成在主表面和背面上的多个导电部分中的一些导电部分，并且由膜形成，半导体芯片安装在封装基板 将半导体芯片与封装基板电连接的导线，设置在封装基板的主面和半导体芯片的主面之间的芯片接合膜，形成在封装的背面的多个焊料凸块 基材和由树脂制成的密封体。 通过在封装基板的主表面和背面上形成由膜形成的干式抗蚀剂膜，可以抑制封装基板的翘曲，因此在回流安装时可能发生封装裂纹 从而提高了半导体器件的可靠性。

公开(公告)号：US07470567B2

公开(公告)日：2008-12-30

申请号：US12078587

申请日：2008-04-02

申请人： Yoshihiko Shimanuki

发明人： Yoshihiko Shimanuki

IPC分类号： H01L21/44

CPC分类号： H01L23/3128 ,  H01L21/561 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/97 ,  H01L2223/54486 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85205 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85986 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H05K3/0052 ,  H05K3/284 ,  H05K2201/09036 ,  H05K2201/0909 ,  H05K2203/0228 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/85186 ,  H01L2224/92247 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554 ,  H01L2224/05599

摘要： A semiconductor device manufacturing method capable of improving the semiconductor device manufacturing yield is disclosed. Semiconductor chips are mounted respectively over semiconductor device regions of a matrix wiring substrate having plural semiconductor device regions, followed by wire bonding, and thereafter sealing resin is formed at a time onto the semiconductor device regions. Thereafter, target marks for dicing are formed on an upper surface of the sealing resin on the basis of target marks pre-formed on an upper surface of the wiring substrate. Then, half-dicing is performed from the upper surface side of the sealing resin 5a on the basis of the target marks for dicing to form grooves whose bottoms reach the wiring substrate. Subsequently, solder balls are connected to a lower surface of the wiring substrate and dicing is performed from a lower surface side of the wiring substrate for division into individual semiconductor devices.

摘要翻译： 公开了能够提高半导体装置的制造成品率的半导体装置的制造方法。 半导体芯片分别安装在具有多个半导体器件区域的矩阵布线基板的半导体器件区域上，然后进行引线接合，然后将树脂一次形成在半导体器件区域上。 此后，基于预先形成在布线基板的上表面上的目标标记，在密封树脂的上表面上形成用于切割的目标标记。 然后，根据切割目标标记，从密封树脂5a的上表面侧进行半切割，形成底部到达布线基板的槽。 随后，将焊锡球连接到布线基板的下表面，并且从布线基板的下表面侧进行切割以分割成单独的半导体器件。

公开(公告)号：US07459347B2

公开(公告)日：2008-12-02

申请号：US12213779

申请日：2008-06-24

申请人： Yoshihiko Shimanuki ,  Masayuki Suzuki

发明人： Yoshihiko Shimanuki ,  Masayuki Suzuki

IPC分类号： H01L21/00

CPC分类号： H01L24/32 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/05554 ,  H01L2224/29007 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85464 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/3512

摘要： A non-leaded resin-sealed semiconductor device is manufactured by the steps of providing a conductive flat substrate (metal plate) of copper plate or the like, fixing semiconductor elements respectively to predetermined positions on the principal surface of the substrate by an insulating adhesive, electrically connecting electrodes on the surfaces of the semiconductor elements with predetermined partition parts of the substrate separate from the semiconductor elements by conductive wires, forming an insulating resin layer on the principal surface of the substrate to cover the semiconductor elements and wires, selectively removing the substrate from the rear of said substrate to form electrically independent partition parts whereof at least some are external electrode terminals, and selectively removing said resin layer to fragment the device into regions containing the semiconductor elements and the plural partition parts around the semiconductor elements. Thus, there is provided a compact non-leaded semiconductor device having a large number of electrode terminals.

摘要翻译： 非导电树脂密封半导体器件通过以下步骤制造：提供铜板等的导电平面基板（金属板），通过绝缘粘合剂将半导体元件分别固定在基板的主表面上的预定位置， 将半导体元件的表面上的电极与基板的预定分隔部分用导电线与半导体元件分开，在基板的主表面上形成绝缘树脂层以覆盖半导体元件和导线，选择性地去除基板 从所述基板的后部形成电气独立的分隔部，其中至少一些是外部电极端子，并且选择性地去除所述树脂层以将器件分解成包含半导体元件的区域和围绕半导体元件的多个分隔部分。 因此，提供了具有大量电极端子的紧凑的非铅半导体器件。