公开(公告)号：US09559065B2

公开(公告)日：2017-01-31

申请号：US14476241

申请日：2014-09-03

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Irmgard Escher-Poeppel ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/07 ,  H01L25/00 ,  H01L23/051 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor arrangement includes upper and lower contact plates and basic chip assemblies. Each chip assembly has a semiconductor chip having a semiconductor body with upper and lower spaced apart sides. An individual upper main electrode and an individual control electrode are arranged on the upper side. The chip assemblies have either respectively a separate lower main electrode arranged on the lower side of the semiconductor chip of the corresponding basic chip assembly, or a common lower main electrode, which for each of the chip assemblies is arranged on the lower side of the semiconductor body of that chip assembly. An electrical current between the individual upper main electrode and the individual or common lower main electrode is controllable by its control electrode. The chip assemblies are connected to one another with a material bonded connection by a dielectric embedding compound, forming a solid assembly.

公开(公告)号：US20170025357A1

公开(公告)日：2017-01-26

申请号：US14808798

申请日：2015-07-24

Applicant: Infineon Technologies AG

Inventor： Peter Ossimitz ,  Gottfried Beer ,  Juergen Hoegerl ,  Andreas Munding

IPC: H01L23/538 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L23/5386 ,  H01L22/32 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/14142 ,  H01L2224/14143 ,  H01L2224/16057 ,  H01L2224/16105 ,  H01L2224/16106 ,  H01L2224/17051 ,  H01L2224/171 ,  H01L2224/17106 ,  H01L2225/06513 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor chip includes a semiconductor body having an active device region, one or more metallization layers insulated from the semiconductor body and configured to carry one or more of ground, power and signals to the active device region, and a plurality of contact terminals formed in or disposed on an outermost one of the metallization layers and configured to provide external electrical access to the semiconductor chip. A minimum distance between adjacent ones of the contact terminals is defined for the semiconductor chip. One or more groups of adjacent ones of the contact terminals have an electrical or functional commonality and a pitch less than the defined minimum distance. A single shared solder joint can connect two or more of the contact terminals of the semiconductor chip to one or more of contact terminals of a substrate such as a circuit board, an interposer or another semiconductor chip.

Abstract translation: 半导体芯片包括具有有源器件区域的半导体本体，与半导体本体绝缘的一个或多个金属化层，并且被配置为将一个或多个接地，功率和信号传送到有源器件区域，以及多个接触端子形成在 或设置在最外面的一个金属化层上并被配置为提供对半导体芯片的外部电接入。 为半导体芯片定义相邻接触端子之间的最小距离。 接触端子中的一组或多组相邻接触端子具有电气或功能通用性以及小于限定的最小距离的间距。 单个共用焊点可以将半导体芯片的两个或更多个接触端子连接到诸如电路板，插入器或其它半导体芯片的衬底的一个或多个接触端子。

公开(公告)号：US09553208B2

公开(公告)日：2017-01-24

申请号：US14027710

申请日：2013-09-16

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Volker Strutz ,  Horst Theuss

IPC: H01L29/82 ,  G01R19/00 ,  G01R33/00 ,  H01L21/56 ,  H01L23/29 ,  H01L23/528

CPC classification number: H01L29/82 ,  G01R15/207 ,  G01R19/0092 ,  G01R33/0047 ,  G01R33/0052 ,  H01L21/561 ,  H01L21/568 ,  H01L23/293 ,  H01L23/3121 ,  H01L23/528 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2924/19105

Abstract: A current sensor device for sensing a measuring current includes a semiconductor chip having a magnetic field sensitive element. The current sensor device further includes an encapsulant embedding the semiconductor chip. A conductor configured to carry the measuring current is electrically insulated from the magnetic field sensitive element. A redistribution structure includes a first metal layer having a first structured portion which forms part of the conductor.

Abstract translation: 用于感测测量电流的电流传感器装置包括具有磁场敏感元件的半导体芯片。 电流传感器装置还包括嵌入半导体芯片的密封剂。 构造成承载测量电流的导体与磁场敏感元件电绝缘。 再分布结构包括具有形成导体的一部分的第一结构化部分的第一金属层。

公开(公告)号：US09390973B2

公开(公告)日：2016-07-12

申请号：US14505270

申请日：2014-10-02

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Barth ,  Jens Pohl ,  Gottfried Beer ,  Heinrich Koerner

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/552 ,  H01L23/66 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/76879 ,  H01L23/481 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6688 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.

Abstract translation: 公开了一种片上系统的结构以及片上系统的形成方法。 在一个实施例中，一种制造片上系统的方法包括从衬底的背面形成穿透衬底开口，穿过衬底开口设置在第一和第二区域之间，第一区域包括用于RF电路的装置，第二区域包括第二 区域包括用于其他电路的装置。 该方法还包括在光致抗蚀剂层上形成用于再分配线的图案，设置在背面下方的光致抗蚀剂层，以及用导电材料填充贯通基板开口和再分配线图案。

公开(公告)号：US20150317553A1

公开(公告)日：2015-11-05

申请号：US14697664

申请日：2015-04-28

Applicant: Infineon Technologies AG

Inventor： Frank Pueschner ,  Thomas Spoettl ,  Jens Pohl ,  Gottfried Beer

IPC: G06K19/077 ,  H01L25/00 ,  G06K19/07

CPC classification number: G06K19/07705 ,  G06K19/0716 ,  G06K19/077 ,  G06K19/07749 ,  G06K19/07754 ,  H01L21/48 ,  H01L23/488 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16238

Abstract: In various embodiments, a smart card module is provided. The smart card module includes a carrier having a first main surface and a second main surface opposite the first main surface. The carrier has at least one plated-through hole. The smart card module further includes a contact array arranged above the first main surface of the carrier and having a plurality of electrical contacts. At least one electrical contact of the plurality of electrical contacts is electrically connected to the plated-through hole. The smart card module further includes a chip arranged above the second main surface. The chip is electrically coupled to at least one electrical contact of the plurality of electrical contacts by the plated-through hole. The smart card module further includes at least one optoelectronic component arranged above the second main surface and electrically conductively connected to the chip.

Abstract translation: 在各种实施例中，提供智能卡模块。 智能卡模块包括具有第一主表面和与第一主表面相对的第二主表面的载体。 载体具有至少一个电镀通孔。 智能卡模块还包括布置在载体的第一主表面上方并具有多个电触点的接触阵列。 多个电触点中的至少一个电接触电连接到电镀通孔。 智能卡模块还包括布置在第二主表面上方的芯片。 芯片通过电镀通孔与多个电触点的至少一个电接触电耦合。 所述智能卡模块还包括布置在所述第二主表面上方并与所述芯片导电连接的至少一个光电子部件。

公开(公告)号：US20150170835A1

公开(公告)日：2015-06-18

申请号：US14571316

申请日：2014-12-16

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Bernhard Knott ,  Rainer Leuschner

IPC: H01F41/02 ,  H01F27/28 ,  H01F27/29 ,  H01F27/255

CPC classification number: H01F41/0206 ,  H01F17/0013 ,  H01F41/046 ,  H01F2017/0066 ,  H01L23/645 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/13055 ,  H01L2924/15311 ,  H01L2924/19042 ,  H01L2924/19105 ,  Y10T29/4902 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: A method for manufacturing an inductor core is developed, wherein the method comprises the following: Forming a first electrical conductor on a first surface of a plate-shaped magnetic core; forming a second electrical conductor on a second surface of the plate-shaped magnetic core, which is opposite the first surface; and forming the inductor core by dicing the plate-shaped magnetic core transverse to the first electrical conductor and second electrical conductor.

Abstract translation: 开发了用于制造电感器芯的方法，其中所述方法包括以下步骤：在板状磁芯的第一表面上形成第一电导体; 在与所述第一表面相对的所述板状磁芯的第二表面上形成第二电导体; 以及通过横切所述第一电导体和第二电导体切割所述板状磁芯而形成所述电感器芯。

公开(公告)号：US20150145149A1

公开(公告)日：2015-05-28

申请号：US14090570

申请日：2013-11-26

Applicant: Infineon Technologies AG

Inventor： Ulrich Wachter ,  Eva Wagner ,  Gottfried Beer

IPC: H01L23/544 ,  H01L21/78 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/544 ,  B23K26/364 ,  B23K26/40 ,  B23K26/402 ,  B23K2103/08 ,  B23K2103/10 ,  B23K2103/12 ,  B23K2103/14 ,  B23K2103/172 ,  B23K2103/26 ,  B23K2103/30 ,  B23K2103/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2223/54433 ,  H01L2223/6677 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device package includes encapsulating at least partially a plurality of semiconductor chips with encapsulating material to form an encapsulation body. The encapsulation body has a first main surface and a second main surface. At least one of a metal layer and an organic layer is formed over the first main surface of the encapsulation body. At least one trace of the at least one of the metal layer and the organic layer is removed by laser ablation. The encapsulation body is then separated into a plurality of semiconductor device packages along the at least one trace.

Abstract translation: 一种制造半导体器件封装的方法包括至少部分地用封装材料封装多个半导体芯片以形成封装体。 封装体具有第一主表面和第二主表面。 金属层和有机层中的至少一个形成在封装体的第一主表面上。 通过激光烧蚀去除金属层和有机层中的至少一个的至少一个迹线。 然后将封装体沿着至少一个迹线分离成多个半导体器件封装。

公开(公告)号：US09041505B2

公开(公告)日：2015-05-26

申请号：US14024395

申请日：2013-09-11

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Urs Elrod ,  Christiane Brunner ,  Thomas Kilger

IPC: H01F27/29 ,  H01F5/00 ,  H01F7/06 ,  H01F27/28 ,  H01F41/04

CPC classification number: H01F27/2804 ,  H01F41/041 ,  H01F2027/2819 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/645 ,  H01L24/19 ,  H01L2224/12105 ,  Y10T29/4902 ,  Y10T29/49071

Abstract: In accordance with an embodiment, a transformer includes a first coil disposed in a first conductive layer on a first side of a first dielectric layer, and a second coil disposed in a second conductive layer on a second side of the first dielectric layer. Each coil has a first end disposed inside its respective coil and a second end disposed at an outer perimeter of its respective coil. A first crossover disposed in the second conductive layer is directly connected to the first end of the first coil and extends past the outer perimeter of the first coil. In addition, a second crossover disposed in the first conductive layer is directly connected to the first end of the second coil and extends past the outer perimeter of the second coil.

Abstract translation: 根据实施例，变压器包括设置在第一电介质层的第一侧上的第一导电层中的第一线圈和设置在第一电介质层的第二侧上的第二导电层中的第二线圈。 每个线圈具有设置在其相应线圈内部的第一端和设置在其相应线圈的外周边的第二端。 设置在第二导电层中的第一交叉直接连接到第一线圈的第一端并延伸超过第一线圈的外周。 此外，设置在第一导电层中的第二交叉直接连接到第二线圈的第一端并且延伸超过第二线圈的外周。

公开(公告)号：US08990744B2

公开(公告)日：2015-03-24

申请号：US13863740

申请日：2013-04-16

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Dominic Maier ,  Gerhard Metzger-Brückl ,  Rainer Leuschner

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5081

Abstract: The capacitance or inductance of electrical circuits is adjusted by measuring inductance or capacitance values of passive components fabricated on a first substrate, storing individual associations between the passive components and the respective measured values of the passive components, and determining electrical connections for the passive components based on the stored individual associations between the passive components and the respective measured values of the passive components. A corresponding system includes a tester operable to measure inductance or capacitance values of the passive components fabricated on the first substrate, a storage system operable to store the individual associations between the passive components and the respective measured values of the passive components, and a processing circuit operable to determine the electrical connections for the passive components based on the stored individual associations between the passive components and the respective measured values of the passive components.

Abstract translation: 通过测量在第一基板上制造的无源部件的电感或电容值来调节电路的电容或电感，存储无源元件之间的各个关联以及无源元件的相应测量值，以及确定基于无源元件的电连接 关于无源部件之间存储的各个关联以及被动部件的相应测量值。 相应的系统包括可操作以测量制造在第一基板上的无源部件的电感或电容值的测试器，可操作以存储无源部件之间的各个关联和无源部件的相应测量值的存储系统，以及处理电路 可操作以基于所存储的无源组件之间的各个关联和无源组件的相应测量值来确定无源组件的电连接。

公开(公告)号：US20150061100A1

公开(公告)日：2015-03-05

申请号：US14477386

申请日：2014-09-04

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Irmgard Escher-Poeppel ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L25/07 ,  H01L23/495 ,  H01L23/492 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/072 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/48 ,  H01L23/492 ,  H01L23/49562 ,  H01L23/562 ,  H01L24/24 ,  H01L24/33 ,  H01L24/72 ,  H01L24/82 ,  H01L24/83 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/29011 ,  H01L2224/32245 ,  H01L2224/82039 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/2064 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2924/00

Abstract: A semiconductor arrangement includes top and bottom contact plates, a plurality of chip assemblies, a dielectric embedding compound, and a control electrode interconnection structure. Each chip assembly has a semiconductor chip having a semiconductor body. The semiconductor body has a top side and an opposing underside. The top side is spaced apart from the underside in a vertical direction. Each semiconductor chip has a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, a control electrode arranged at the top side, and an electrically conductive top compensation die, arranged on the side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode by means of a top connecting layer. An electric current between the top main electrode and the bottom main electrode can be controlled by means of the control electrode.

Abstract translation: 半导体装置包括顶部和底部接触板，多个芯片组件，电介质嵌入化合物和控制电极互连结构。 每个芯片组件具有半导体芯片，该半导体芯片具有半导体本体。 半导体本体具有顶侧和相对的下侧。 顶侧在垂直方向上与下侧隔开。 每个半导体芯片具有布置在顶侧的顶部主电极，设置在下侧的底部主电极，布置在顶侧的控制电极和布置在顶部主电极对面侧的导电顶部补偿裸片 远离半导体本体并且通过顶部连接层内导电地连接到顶部主电极。 可以通过控制电极来控制顶部主电极和底部主电极之间的电流。