公开(公告)号：US07470990B2

公开(公告)日：2008-12-30

申请号：US11086323

申请日：2005-03-23

申请人： Robert M. Japp ,  Irving Memis ,  Kostas I. Papathomas

发明人： Robert M. Japp ,  Irving Memis ,  Kostas I. Papathomas

IPC分类号： H01L23/52

CPC分类号： H01L23/3735 ,  H01L23/145 ,  H01L23/3733 ,  H01L23/4922 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/564 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0366 ,  H05K1/0373 ,  H05K3/4602 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K3/4688 ,  H05K2201/0209 ,  H05K2201/0278 ,  H05K2201/068

摘要： A circuitized substrate including a composite layer including a first dielectric sub-layer including a plurality of fibers having a low coefficient of thermal expansion and a second dielectric sub-layer of a low moisture absorptivity resin, the second dielectric sub-layer not including continuous or semi-continuous fibers or the like as part thereof. The substrate further includes at least one electrically conductive layer as part thereof. An electrical assembly and a method of making the substrate are also provided, as is an information handling system (e.g., computer) incorporating the circuitized substrate of the invention as part thereof.

摘要翻译： 一种电路化基板，包括复合层，所述复合层包括第一介电子层，所述第一介电子层包括具有低热膨胀系数的多个纤维和低吸湿性树脂的第二介电子层，所述第二介电子层不包括连续的或 半连续纤维等作为其一部分。 衬底还包括至少一个作为其一部分的导电层。 还提供电气组件和制造基板的方法，如本发明的电路化基板作为其一部分的信息处理系统（例如，计算机）。

公开(公告)号：US07429789B2

公开(公告)日：2008-09-30

申请号：US11390386

申请日：2006-03-28

申请人： Robert M. Japp ,  Voya R. Markovich ,  Kostas I. Papathomas

发明人： Robert M. Japp ,  Voya R. Markovich ,  Kostas I. Papathomas

IPC分类号： H01L21/31 ,  H01L23/48

CPC分类号： H01L23/145 ,  H01L21/44 ,  H01L21/48 ,  H01L23/4922 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L29/40 ,  H01L2924/0002 ,  H05K1/0373 ,  H05K3/4602 ,  H05K2201/015 ,  H05K2201/0209 ,  Y10T428/1303 ,  H01L2924/00

摘要： A dielectric composition for forming a dielectric layer usable in circuitized substrates such as PCBs, chip carriers and the like, the composition including at least two fluoropolymers and two inorganic fillers. A circuitized substrate including at least one such dielectric layer and at least one conductive layer thereon is also provided.

摘要翻译： 一种电介质组合物，用于形成可用于诸如PCB，芯片载体等的电路化基底中的介电层，所述组合物包含至少两种含氟聚合物和两种无机填料。 还提供了包括至少一个这样的电介质层和其上的至少一个导电层的电路化衬底。

公开(公告)号：US07381587B2

公开(公告)日：2008-06-03

申请号：US11324432

申请日：2006-01-04

申请人： Robert M. Japp ,  John M. Lauffer ,  Voya R. Markovich ,  William E. Wilson

发明人： Robert M. Japp ,  John M. Lauffer ,  Voya R. Markovich ,  William E. Wilson

IPC分类号： H01L21/00

CPC分类号： H05K3/4641 ,  H05K3/429 ,  H05K2203/068

摘要： A method of making a circuitized substrate and an electrical assembly utilizing same in which the substrate is comprised of at least two sub-composites in which the dielectric material of at least one of these sub-composites is heated during bonding (e.g., lamination) to the other sufficiently to cause the dielectric material to flow into and substantially fill openings in a conductive layer for the bonded structure. Conductive thru-holes are formed within the bonded structure to couple selected ones of the structure's conductive layers. Formation of an electrical assembly is possible by positioning one or more electrical components (e.g., semiconductor chips or chip carriers) on the final structure and electrically coupling these to the structure's external circuitry.

摘要翻译： 一种制造电路化基板的方法和使用其的电气组件，其中基板由至少两个亚复合材料构成，其中这些亚复合材料中的至少一个的介电材料在粘合（例如，层压）期间被加热到 另一个足以使电介质材料流入并基本上填充用于接合结构的导电层中的开口。 导电通孔形成在接合结构内，以耦合所选择的结构导电层。 通过将一个或多个电气部件（例如，半导体芯片或芯片载体）定位在最终结构上并将其电耦合到结构的外部电路，可以形成电组件。

公开(公告)号：US20080078570A1

公开(公告)日：2008-04-03

申请号：US11541776

申请日：2006-10-03

申请人： Robert M. Japp ,  Voya R. Markovich ,  Kostas I. Papthomas

发明人： Robert M. Japp ,  Voya R. Markovich ,  Kostas I. Papthomas

IPC分类号： H05K1/09 ,  H05K3/36

CPC分类号： H05K3/4688 ,  H01L23/145 ,  H01L23/3733 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0366 ,  H05K1/0373 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0209 ,  H05K2201/0278 ,  H05K2201/09309 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  H01L2224/0401

摘要： A circuitized substrate including a composite layer comprising a first dielectric sub-layer comprised of a halogen-free resin and fibers dispersed therein and a second dielectric sub-layer without fibers but also including a halogen-free resin with inorganic particulates therein. A method of making such a substrate is also provided, as is a multilayered assembly including one or more such circuitized substrates, possibly in combination with other substrates. An information handling system designed for having one or more such circuitized substrates is also provided.

摘要翻译： 一种电路化基板，包括复合层，该复合层包括由不含卤素的树脂和分散在其中的纤维构成的第一介电子层和不含纤维的第二电介质子层，并且还包括无卤素树脂和无机颗粒。 还提供了制造这种基板的方法，以及包括一个或多个这样的电路化基板的多层组件，可能与其它基板组合。 还提供了设计用于具有一个或多个这样的电路化基板的信息处理系统。

公开(公告)号：US07070909B2

公开(公告)日：2006-07-04

申请号：US10928178

申请日：2004-08-30

申请人： Robert M. Japp ,  Pamela Lulkoski ,  Jeffrey McKeveny ,  Jan Obrzut ,  Kenneth Lynn Potter

发明人： Robert M. Japp ,  Pamela Lulkoski ,  Jeffrey McKeveny ,  Jan Obrzut ,  Kenneth Lynn Potter

IPC分类号： H05K3/00 ,  H05K1/03

CPC分类号： D03D1/0082 ,  B32B5/26 ,  B32B17/04 ,  C03C25/42 ,  D03D15/0011 ,  H05K1/0366 ,  H05K3/0082 ,  H05K2201/0112 ,  H05K2201/029 ,  Y10S428/901 ,  Y10T156/10 ,  Y10T428/31525 ,  Y10T442/2008 ,  Y10T442/2926 ,  Y10T442/2951 ,  Y10T442/2992 ,  Y10T442/3976

摘要： The glass transmittance of UV light having a wavelength of 365 nanometers is reduced by compounding an oxide or salt of at least one of Fe, Cu, Cr, Ce, Mn and mixtures thereof. The fiberglass cloth can be used for providing reinforced prepregs used in producing printed circuit boards or laminated chip carrier substrates.

摘要翻译： 通过配合Fe，Cu，Cr，Ce，Mn及其混合物中的至少一种的氧化物或盐来减少波长为365纳米的UV光的玻璃透射率。 玻璃纤维布可用于制造用于制造印刷电路板或层压芯片载体基板的增强预浸料。

公开(公告)号：US06829823B2

公开(公告)日：2004-12-14

申请号：US10067551

申请日：2002-02-05

申请人： Francis J. Downes, Jr. ,  Donald S. Farquhar ,  Elizabeth Foster ,  Robert M. Japp ,  Gerald W. Jones ,  John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

发明人： Francis J. Downes, Jr. ,  Donald S. Farquhar ,  Elizabeth Foster ,  Robert M. Japp ,  Gerald W. Jones ,  John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

IPC分类号： H01K310

CPC分类号： H05K3/4641 ,  H01L21/4853 ,  H01L23/3735 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/0401

摘要： A method of making a multi-layered interconnect structure. First and second electrically conductive members are formed on the first and second dielectric layers, respectively. The dielectric layer are formed on opposing surfaces of a thermally conductive layer. A first and second electrically conductive layer is formed within the first dielectric layer. The second electrically conductive layer includes shielded signal conductors and is positioned between the first electrically conductive layer and the thermally conductive layer. A plated through hole (PTH) formed through the interconnect structure is electrically connected to one of the first and second electrically conductive members and to one of the shielded signal conductors. A third dielectric layer, formed on the first dielectric layer and on portions of the first electrically conductive members, substantially overlies the PTH and includes a high density interconnect layer for providing an electrical path from an electronic device to the shielded signal conductors.

摘要翻译： 一种制造多层互连结构的方法。 第一和第二导电构件分别形成在第一和第二电介质层上。 电介质层形成在导热层的相对表面上。 第一和第二导电层形成在第一介电层内。 第二导电层包括屏蔽信号导体并且位于第一导电层和导热层之间。 通过互连结构形成的电镀通孔（PTH）电连接到第一和第二导电构件中的一个和屏蔽信号导体之一。 形成在第一介电层上和第一导电构件的部分上的第三电介质层基本上覆盖在PTH上，并且包括用于提供从电子器件到屏蔽信号导体的电气路径的高密度互连层。

公开(公告)号：US06820332B2

公开(公告)日：2004-11-23

申请号：US10196993

申请日：2002-07-16

申请人： Robert M. Japp ,  Voya R. Markovich ,  Konstantinos I. Papathomas

发明人： Robert M. Japp ,  Voya R. Markovich ,  Konstantinos I. Papathomas

IPC分类号： H01K310

CPC分类号： H05K3/382 ,  H05K1/056 ,  H05K3/383 ,  H05K3/384 ,  H05K3/388 ,  H05K3/389 ,  H05K3/445 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2203/0307 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A substrate and a method of making the substrate is provided. The substrate includes a layer of metal with at least one through hole therein, the layer of metal having an adhesion promoting layer thereon. A layer of a partially cured low-loss polymer or polymer precursor is positioned on the adhesion promoting layer and a plurality of conductive circuit lines are positioned on a portion of the partially cured dielectric layer. The substrate can be used as a building block in the fabrication of a multilayered printed circuit board.

摘要翻译： 提供了基板和制造基板的方法。 衬底包括金属层，其中具有至少一个通孔，金属层在其上具有粘附促进层。 部分固化的低损失聚合物或聚合物前体层位于粘附促进层上，并且多个导电电路线位于部分固化的介电层的一部分上。 衬底可以用作制造多层印刷电路板的构件。

公开(公告)号：US06790305B2

公开(公告)日：2004-09-14

申请号：US10266652

申请日：2002-10-08

申请人： Brian E. Curcio ,  Frank D. Egitto ,  Robert M. Japp ,  Thomas R. Miller ,  Manh-Quan T. Nguyen ,  Douglas O. Powell

发明人： Brian E. Curcio ,  Frank D. Egitto ,  Robert M. Japp ,  Thomas R. Miller ,  Manh-Quan T. Nguyen ,  Douglas O. Powell

IPC分类号： B32B3114

CPC分类号： H01L21/486 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/462 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/0191 ,  H05K2203/0264 ,  H05K2203/061 ,  H05K2203/1152 ,  Y10S438/976 ,  Y10T29/49165 ,  Y10T428/24917 ,  Y10T428/28 ,  Y10T428/2804 ,  Y10T428/2839 ,  Y10T428/2848

摘要： A method for producing small pitch z-axis electrical interconnections in layers of dielectric materials which are applied to printed wiring boards and diverse electronic packages. A method for parallel fabrication of intermediate structures which are subsequently jointed to form a final structure. In addition there is provided a z-interconnected electrical structure, employing dielectric materials such as resin coated copper, employable in the manufacture of diverse type of electronic packages, including printed wiring boards (PWBs), substrates, multi-chip modules and the like.

摘要翻译： 一种用于在印刷电路板和各种电子封装上施加介电材料层的小间距z轴电互连的方法。 一种用于平行制造中间结构的方法，其随后连接以形成最终结构。 此外，提供了一种采用诸如树脂涂覆铜之类的介电材料的z互连电结构，可用于制造包括印刷线路板（PWB），基板，多芯片模块等的各种类型的电子封装。

公开(公告)号：US06700078B2

公开(公告)日：2004-03-02

申请号：US10176254

申请日：2002-06-19

申请人： Donald S. Farquhar ,  Robert M. Japp ,  John M. Lauffer ,  Konstantinos I. Papathomas

发明人： Donald S. Farquhar ,  Robert M. Japp ,  John M. Lauffer ,  Konstantinos I. Papathomas

IPC分类号： H05K116

CPC分类号： H05K3/429 ,  H05K2201/0187 ,  H05K2201/096 ,  H05K2201/09645 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917

摘要： A method and structure relating to multisegmented plated through holes. A substrate includes a dielectric layer sandwiched between a first laminate layer and a second laminate layer. A through hole is formed through the substrate. The through hole passes through nonplatable dielectric material within the dielectric layer. As a result, subsequent seeding and electroplating of the through hole results in a conductive metal plating forming at a wall of the through hole on a segment of the first laminate layer and on a segment of the second laminate layer, but not on the nonplatable dielectric material of the dielectric layer. Thus, the conductive metal plating is not continuous from the first laminate layer to the second laminate layer.

摘要翻译： 涉及多段电镀通孔的方法和结构。 基板包括夹在第一层叠层和第二层叠层之间的电介质层。 穿过基板形成通孔。 通孔穿过介电层内的不可电介质材料。 结果，随后的通孔的接种和电镀导致在第一层压层的段上的通孔的壁上和第二层压层的段上形成导电金属电镀，而不在不可电绝缘的电介质 电介质层的材料。 因此，导电金属电镀从第一层叠层到第二层叠层不是连续的。

公开(公告)号：US06207595B1

公开(公告)日：2001-03-27

申请号：US09033505

申请日：1998-03-02

申请人： Bernd K. Appelt ,  Lawrence R. Blumberg ,  William T. Fotorny ,  Ross D. Havens ,  Robert M. Japp ,  Kostas Papathomas ,  Jan Obrzut ,  Mark D. Poliks ,  Amarjit S. Rai

发明人： Bernd K. Appelt ,  Lawrence R. Blumberg ,  William T. Fotorny ,  Ross D. Havens ,  Robert M. Japp ,  Kostas Papathomas ,  Jan Obrzut ,  Mark D. Poliks ,  Amarjit S. Rai

IPC分类号： B32B2704

CPC分类号： H01L23/564 ,  H01L23/08 ,  H01L23/145 ,  H01L2924/0002 ,  H05K1/0366 ,  H05K2201/029 ,  H05K2201/0761 ,  Y10T442/2475 ,  Y10T442/2959 ,  Y10T442/2992 ,  H01L2924/00

摘要： A fabric material and method of its manufacture suitable for use in electronic packages including chip carriers. High insulation resistance is exhibited when subjected to high temperatures and humidity stress conditions.

摘要翻译： 一种其制造的织物材料及其制造方法，其适用于包括芯片载体的电子封装。 当受到高温和高湿度条件的影响时，表现出高的绝缘电阻。