公开(公告)号：US09607958B2

公开(公告)日：2017-03-28

申请号：US14512614

申请日：2014-10-13

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L24/14 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0348 ,  H01L2224/0361 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13008 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/20101 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.

公开(公告)号：US09559039B2

公开(公告)日：2017-01-31

申请号：US13800807

申请日：2013-03-13

Applicant: STATS ChipPAC, Ltd.

Inventor： Il Kwon Shim ,  Jun Mo Koo ,  Pandi C. Marimuthu ,  Yaojian Lin ,  See Chian Lim

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01082 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a substrate including a base and a plurality of conductive posts extending from the base. The substrate can be a wafer-shape, panel, or singulated form. The conductive posts can have a circular, rectangular, tapered, or narrowing intermediate shape. A semiconductor die is disposed through an opening in the base between the conductive posts. The semiconductor die extends above the conductive posts or is disposed below the conductive posts. An encapsulant is deposited over the semiconductor die and around the conductive posts. The base and a portion of the encapsulant is removed to electrically isolate the conductive posts. An interconnect structure is formed over the semiconductor die, encapsulant, and conductive posts. An insulating layer is formed over the semiconductor die, encapsulant, and conductive posts. A semiconductor package is disposed over the semiconductor die and electrically connected to the conductive posts.

Abstract translation: 半导体器件具有包括基底和从基底延伸的多个导电柱的基底。 衬底可以是晶片形状，面板或单体形式。 导电柱可以具有圆形，矩形，锥形或变窄的中间形状。 通过导电柱之间的底座中的开口设置半导体管芯。 半导体管芯延伸到导电柱之上，或者设置在导电柱的下方。 密封剂沉积在半导体管芯上并且在导电柱周围。 去除基底和一部分密封剂以电绝缘导电柱。 在半导体管芯，密封剂和导电柱上形成互连结构。 在半导体管芯，密封剂和导电柱上形成绝缘层。 半导体封装设置在半导体管芯上并电连接到导电柱。

公开(公告)号：US20160276307A1

公开(公告)日：2016-09-22

申请号：US14660840

申请日：2015-03-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L25/16 ,  H01L23/552 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L25/00 ,  H01L21/66

CPC classification number: H01L24/17 ,  H01L21/561 ,  H01L21/568 ,  H01L22/14 ,  H01L23/13 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/3737 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17515 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.

Abstract translation: PoP半导体器件具有设置在底部半导体封装上的顶部半导体封装。 顶部半导体封装具有衬底和设置在衬底上的第一半导体管芯。 第一和第二密封剂沉积在第一半导体管芯和衬底上。 在沉积第二密封剂之后，在衬底上形成第一叠层互连结构。 顶部包装被放置在底部包装上。 底部封装具有设置在第二半导体管芯周围的第二半导体管芯和模块化互连单元。 在第二半导体管芯和模块化互连单元上形成第二堆叠互连结构。 模块化互连单元包括多个导电通孔和电连接到导电通孔的多个接触垫。 顶部半导体封装上的积聚互连结构的I / O图案被设计成与模块化互连单元的I / O模式一致。

公开(公告)号：US20160214857A1

公开(公告)日：2016-07-28

申请号：US15008347

申请日：2016-01-27

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Il Kwon Shim

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81B2201/0257 ,  B81B2207/012 ,  B81B2207/096 ,  H01L2224/48091 ,  H01L2924/15151 ,  H01L2924/00014

Abstract: A microelectromechanical system (MEMS) semiconductor device has a first and second semiconductor die. A first semiconductor die is embedded within an encapsulant together with a modular interconnect unit. Alternatively, the first semiconductor die is embedded within a substrate. A second semiconductor die, such as a MEMS die, is disposed over the first semiconductor die and electrically connected to the first semiconductor die through an interconnect structure. In another embodiment, the first semiconductor die is flip chip mounted to the substrate, and the second semiconductor die is wire bonded to the substrate adjacent to the first semiconductor die. In another embodiment, first and second semiconductor die are embedded in an encapsulant and are electrically connected through a build-up interconnect structure. A lid is disposed over the semiconductor die. In a MEMS microphone embodiment, the lid, substrate, or interconnect structure includes an opening over a surface of the MEMS die.

Abstract translation: 微机电系统（MEMS）半导体器件具有第一和第二半导体管芯。 第一半导体管芯与模块化互连单元一起嵌入密封剂内。 或者，第一半导体管芯被嵌入到衬底内。 第二半导体管芯，例如MEMS管芯，设置在第一半导体管芯上，并通过互连结构电连接到第一半导体管芯。 在另一个实施例中，第一半导体管芯是倒装芯片安装到衬底，并且第二半导体管芯与第一半导体管芯相邻的衬底引线接合。 在另一个实施例中，第一和第二半导体管芯被嵌入密封剂中并通过堆积互连结构电连接。 盖子设置在半导体管芯上。 在MEMS麦克风实施例中，盖，基板或互连结构包括在MEMS管芯的表面上的开口。

公开(公告)号：US09385102B2

公开(公告)日：2016-07-05

申请号：US13630912

申请日：2012-09-28

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Yu Gu

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/3128 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/315 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/03

Abstract: A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die. A build-up interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A first supporting layer is formed over a second surface of the semiconductor die as a supporting substrate or silicon wafer disposed opposite the build-up interconnect structure. A second supporting layer is formed over the first supporting layer an includes a fiber enhanced polymer composite material comprising a footprint including an area greater than or equal to an area of a footprint of the semiconductor die. The semiconductor die comprises a thickness less than 450 micrometers (μm). The thickness of the semiconductor die is at least 1 μm less than a difference between a total thickness of the semiconductor device and a thickness of the build-up interconnect structure and the second supporting layer.

Abstract translation: 半导体器件包括半导体管芯。 在半导体管芯周围形成密封剂。 在半导体管芯和密封剂的第一表面上形成积聚互连结构。 第一支撑层形成在半导体管芯的第二表面上，作为与积聚互连结构相对设置的支撑衬底或硅晶片。 在第一支撑层上形成第二支撑层，包括纤维增强聚合物复合材料，其包括占地面积，该占地面积大于或等于半导体管芯的覆盖区域的面积。 半导体管芯的厚度小于450微米（μm）。 半导体管芯的厚度比半导体器件的总厚度和积层互连结构和第二支撑层的厚度之差小至少1μm。

公开(公告)号：US20160141238A1

公开(公告)日：2016-05-19

申请号：US15007518

申请日：2016-01-27

Applicant: STATS ChipPAC, Ltd.

Inventor： Seung Wook Yoon ,  Jose A. Caparas ,  Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Xusheng Bao ,  Jianmin Fang

IPC: H01L23/498 ,  H01L21/768 ,  H01L21/311 ,  H01L25/10

CPC classification number: H01L23/49827 ,  H01L21/311 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76804 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/19 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant. An opening is formed from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure. A bump is formed recessed within the opening and disposed over the surface of the interconnect structure. A semiconductor package is provided. The semiconductor package is disposed over the second surface of the encapsulant and electrically connected to the bump. A plurality of interconnect structures is formed over the semiconductor package to electrically connect the semiconductor package to the bump. The semiconductor package includes a memory device. The semiconductor device includes a height less than 1 millimeter. The opening includes a tapered sidewall formed by laser direct ablation.

Abstract translation: 半导体器件具有沉积在半导体管芯上方和周围的具有密封剂的半导体管芯。 在密封剂的第一表面上形成互连结构。 开口由密封剂的第二表面形成到密封剂的第一表面以暴露互连结构的表面。 凸起凹陷形成在开口内并设置在互连结构的表面上。 提供半导体封装。 半导体封装设置在密封剂的第二表面上并电连接到凸块。 多个互连结构形成在半导体封装上，以将半导体封装电连接到凸块。 半导体封装包括存储器件。 半导体器件包括高度小于1毫米的半导体器件。 开口包括通过激光直接消融形成的锥形侧壁。

公开(公告)号：US09281259B2

公开(公告)日：2016-03-08

申请号：US14079273

申请日：2013-11-13

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Jose Alvin Caparas ,  Glenn Omandam

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/315 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die mounted to a carrier. A first encapsulant is deposited over the semiconductor die and carrier. A stiffening support member can be disposed over the carrier around the semiconductor die. A plurality of channels or recesses is formed in the first encapsulant. The recesses can be formed by removing a portion of the first encapsulant. Alternatively, the recesses are formed in a chase mold having a plurality of extended surfaces. A second encapsulant can be deposited into the recesses of the first encapsulant. The carrier is removed and an interconnect structure is formed over the semiconductor die and first encapsulant. The thickness of the first encapsulant provides sufficient stiffness to reduce warpage while the recesses provide stress relief during formation of the interconnect structure. A portion of the first encapsulant and recesses are removed to reduce thickness of the semiconductor device.

Abstract translation: 半导体器件具有安装到载体上的半导体管芯。 第一密封剂沉积在半导体管芯和载体上。 加强支撑构件可以设置在半导体管芯周围的载体上。 在第一密封剂中形成多个通道或凹槽。 可以通过去除第一密封剂的一部分来形成凹部。 或者，凹部形成在具有多个延伸表面的追逐模具中。 可以将第二密封剂沉积到第一密封剂的凹部中。 移除载体并且在半导体管芯和第一密封剂上形成互连结构。 第一密封剂的厚度提供足够的刚度以减少翘曲，同时凹槽在形成互连结构期间提供应力释放。 去除第一密封剂和凹部的一部分以减小半导体器件的厚度。

公开(公告)号：US20160013148A1

公开(公告)日：2016-01-14

申请号：US14861040

申请日：2015-09-22

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen

IPC: H01L23/00

CPC classification number: H01L24/19 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/11 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2924/014

Abstract: A semiconductor device has a build-up interconnect structure including a first insulating layer with a first material and a second insulating layer with a second material. A first conductive layer is formed over the first insulating layer, and the second insulating layer is formed over the first conductive layer. An optional third insulating layer has the second material and is formed over the second insulating layer. A fourth insulating layer has the first material and is formed over the third insulating layer. The second, third, and fourth insulating layers are cured sequentially or simultaneously. The first material includes a greater tensile strength, elastic modulus, and CTE than the second material. The build-up interconnect structure is formed over a semiconductor wafer or semiconductor die in a reconstituted panel. Alternatively, the build-up interconnect structure is formed over a carrier and a semiconductor die is mounted over the build-up interconnect structure.

Abstract translation: 半导体器件具有包括具有第一材料的第一绝缘层和具有第二材料的第二绝缘层的堆积互连结构。 第一导电层形成在第一绝缘层上，第二绝缘层形成在第一导电层上。 可选的第三绝缘层具有第二材料并形成在第二绝缘层上。 第四绝缘层具有第一材料并形成在第三绝缘层上。 第二，第三和第四绝缘层依次或同时固化。 第一种材料比第二种材料具有更大的拉伸强度，弹性模量和CTE。 积层互连结构形成在重构面板中的半导体晶片或半导体晶片上。 或者，积累互连结构形成在载体上，半导体管芯安装在积层互连结构上。

公开(公告)号：US09177930B2

公开(公告)日：2015-11-03

申请号：US13621810

申请日：2012-09-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05001 ,  H01L2224/05016 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05556 ,  H01L2224/05571 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11906 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/136 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014

Abstract: A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer. The intermediate conductive layer is in electrical contact with the contact pad. A copper inner core pillar is formed by plating over the intermediate conductive layer. The inner core pillar has a rectangular, cylindrical, toroidal, or hollow cylinder form factor. A solder bump is formed around the inner core pillar by plating solder material and reflowing the solder material to form the solder bump. A first barrier layer and wetting layer are formed between the inner core pillar and solder bump. The solder bump is in electrical contact with the intermediate conductive layer.

Abstract translation: 倒装芯片半导体封装具有带有多个有源器件的衬底。 接触焊盘形成在与多个有源器件电接触的衬底上。 在基板和中间导电层之间形成钝化层，第二阻挡层和粘附层。 中间导电层与接触垫电接触。 通过在中间导电层上电镀形成铜内核柱。 内芯柱具有矩形，圆柱形，环形或中空圆柱形。 通过电镀焊料材料并回流焊料材料形成焊料凸点，在内芯柱周围形成焊料凸块。 在内芯柱和焊料凸块之间形成第一阻挡层和润湿层。 焊料凸块与中间导电层电接触。

公开(公告)号：US20150155248A1

公开(公告)日：2015-06-04

申请号：US14616942

申请日：2015-02-09

Applicant: STATS CHIPPAC, LTD.

Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang ,  Xia Feng

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/28 ,  H01L21/56

CPC classification number: H01L23/49816 ,  H01L21/56 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76879 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L2223/5448 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/03

Abstract: A semiconductor device comprises a semiconductor die including a conductive layer. A first insulating layer is formed over the semiconductor die and conductive layer. An encapsulant is disposed over the semiconductor die. A compliant island is formed over the first insulating layer. An interconnect structure is formed over the compliant island. An under bump metalization (UBM) is formed over the compliant island. The compliant island includes a diameter greater than 5 μm larger than a diameter of the UBM. An opening is formed in the compliant island over the conductive layer. A second insulating layer is formed over the first insulating layer and compliant island. A third insulating layer is formed over an interface between the semiconductor die and the encapsulant. An opening is formed in the third insulating layer over the encapsulant for stress relief.

Abstract translation: 半导体器件包括具有导电层的半导体管芯。 在半导体管芯和导电层上形成第一绝缘层。 密封剂设置在半导体管芯上。 在第一绝缘层上形成顺应性岛。 互连结构形成在柔性岛上。 凸块金属化（UBM）形成在柔性岛上。 柔性岛包括比UBM的直径大大于5μm的直径。 在导电层上的柔性岛中形成开口。 在第一绝缘层和顺应性岛上形成第二绝缘层。 在半导体管芯和密封剂之间的界面上形成第三绝缘层。 在密封剂上的第三绝缘层中形成开口以消除应力。