公开(公告)号：US20180358312A1

公开(公告)日：2018-12-13

申请号：US16043107

申请日：2018-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01Q21/00

CPC classification number: H01L23/66 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2223/6688 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/214 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01Q1/2283 ,  H01Q21/0087

Abstract: A method of manufacturing a package structure is provided with the following steps, providing a first die, a second die and a third die; forming a first redistribution layer located on and electrically coupled to the first die, the second die and the third die; and forming an antenna located on and electrically coupled to the first die, the second die and the third die, wherein a distance of an electrical connection path between the first die and the antenna is smaller than or equal to a distance of an electrical connection path between the second die and the antenna and a distance of an electrical connection path between the third die and the antenna.

公开(公告)号：US10032722B2

公开(公告)日：2018-07-24

申请号：US15253897

申请日：2016-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/66 ,  H01L25/065 ,  H01L25/00 ,  H01Q1/22

Abstract: A package structure has a first die, a second die, the third die, a molding compound, a first redistribution layer, an antenna and conductive elements. The first die, the second die and the third die are molded in a molding compound. The first redistribution layer is disposed on the molding compound and is electrically connected to the first die, the second die and the third die. The antenna is located on the molding compound and electrically connected to the first die, the second die and the third die, wherein a distance of an electrical connection path between the first die and the antenna is smaller than or equal to a distance of an electrical connection path between the second die and the antenna and a distance of an electrical connection path between the third die and the antenna. The conductive elements are connected to the first redistribution layer, wherein the first redistribution layer is located between the conductive elements and the molding compound.

公开(公告)号：US09966360B2

公开(公告)日：2018-05-08

申请号：US15202541

申请日：2016-07-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Kuo-Chung Yee

IPC: H01L21/00 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L27/146 ,  H01L25/00 ,  H01L21/78 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/683 ,  G06K9/00 ,  H01L21/56

CPC classification number: H01L25/0652 ,  G06K9/00006 ,  H01L21/31051 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3157 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L25/50 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687 ,  H01L2221/68331 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02333

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a first redistribution layer, a first die over the first redistribution layer, a molding compound encapsulating at least one second die and at least one third die disposed on the first redistribution layer, and at least one fourth die and conductive elements connected to the first redistribution layer. Through vias of the first die are electrically connected to through interlayer vias penetrating through the molding compound and are electrically connected to the first redistribution layer. The semiconductor package may further include a second redistribution layer disposed on the molding compound and between the first die, the second die and the third die.

公开(公告)号：US20240250067A1

公开(公告)日：2024-07-25

申请号：US18598250

申请日：2024-03-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Tsung-Ding Wang ,  Chien-Hsun Lee

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76879 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5389 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/08137 ,  H01L2224/08146 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/18162

Abstract: A semiconductor device and a method of making the same are provided. A first die and a second die are placed over a carrier substrate. A first molding material is formed adjacent to the first die and the second die. A first redistribution layer is formed overlying the first molding material. A through via is formed over the first redistribution layer. A package component is on the first redistribution layer next to the copper pillar. The package component includes a second redistribution layer. The package component is positioned so that it overlies both the first die and the second die in part. A second molding material is formed adjacent to the package component and the first copper pillar. A third redistribution layer is formed overlying the second molding material. The second redistribution layer is placed on a substrate and bonded to the substrate.

公开(公告)号：US12040566B2

公开(公告)日：2024-07-16

申请号：US17885380

申请日：2022-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chuei-Tang Wang ,  Chung-Hao Tsai ,  Jeng-Shien Hsieh ,  Wei-Heng Lin ,  Kuo-Chung Yee ,  Chen-Hua Yu

IPC: H01L23/22 ,  H01L23/24 ,  H01Q1/22 ,  H01Q1/36 ,  H01Q1/48 ,  H01Q3/24 ,  H01Q9/06

CPC classification number: H01Q9/065 ,  H01Q1/2283 ,  H01Q1/36 ,  H01Q1/48 ,  H01Q3/24

Abstract: An antenna device includes a radio frequency (RF) die, a first dielectric layer, a feeding line, a ground line, a second dielectric layer, and a radiating element. The first dielectric layer is over the RF die. The feeding line is in the first dielectric layer and is connected to the RF die. The ground line is in the first dielectric layer and is spaced apart from the feeding line. The second dielectric layer covers the first dielectric layer. The radiating element is over the second dielectric layer and is not in physically contact with the feeding line.

公开(公告)号：US12033976B2

公开(公告)日：2024-07-09

申请号：US18164061

申请日：2023-02-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/10 ,  H01L23/36 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76885 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L23/36 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/94 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/82005 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/92225 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2224/82 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/73204 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2924/00

Abstract: An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs.

公开(公告)号：US20240153901A1

公开(公告)日：2024-05-09

申请号：US18151714

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Han-Jong Chia ,  Wei-Ming Wang ,  Kuo-Chung Yee ,  Chen Chen ,  Shih-Peng Tai

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/80 ,  H01L24/13 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05649 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/0568 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/06505 ,  H01L2224/08123 ,  H01L2224/08147 ,  H01L2224/13147 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80896 ,  H01L2924/04642 ,  H01L2924/0544 ,  H01L2924/059

Abstract: A first and second semiconductor device are bonded together using a bonding contact pad embedded within a bonding dielectric layer of the first semiconductor device and at least one bonding via embedded within a bonding dielectric layer of the second semiconductor device. The bonding contact pad extends a first dimension in a first direction perpendicular to the major surface of the first semiconductor device and a second dimension in a second direction parallel to the plane of the first semiconductor wafer, the second dimension being at least twice the first dimension. The bonding via extends a third dimension in the first direction and a fourth dimension in the second direction, the third dimension being at least twice the first dimension. The bonding contact pad and bonding via may be at least partially embedded in respective bonding dielectric layers in respective topmost dielectric layers of respective stacked interconnect layers.

公开(公告)号：US20240047216A1

公开(公告)日：2024-02-08

申请号：US17816782

申请日：2022-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ming Wang ,  Yu-Hung Lin ,  Shih-Peng Tai ,  Kuo-Chung Yee

IPC: H01L21/308 ,  H01L21/311 ,  H01L23/00

CPC classification number: H01L21/308 ,  H01L21/31144 ,  H01L24/80 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A method includes forming an etching mask over a first wafer. The etching mask covers an inner portion of the first wafer. A wafer edge trimming process is performed to trim an edge portion of the first wafer, with the etching mask protecting the inner portion of the first wafer from being etched. The edge portion forms a full ring encircling the inner portion of the first wafer. The method further includes removing the etching mask, and bonding the first wafer to a second wafer.

公开(公告)号：US20240014091A1

公开(公告)日：2024-01-11

申请号：US17861556

申请日：2022-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Wei-Ming Wang ,  Yu-Hung Lin ,  Shih-Peng Tai ,  Kuo-Chung Yee

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/367 ,  H01L24/08 ,  H01L23/481 ,  H01L25/0657 ,  H01L24/05 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08245 ,  H01L2224/06181 ,  H01L2224/0557 ,  H01L2224/80896 ,  H01L24/80 ,  H01L24/32 ,  H01L2224/32245 ,  H01L2224/2929 ,  H01L2224/29393 ,  H01L2224/29193 ,  H01L24/29 ,  H01L23/3675 ,  H01L2225/06589

Abstract: A semiconductor device includes an integrated circuit structure and a thermal pillar over the integrated circuit structure. The integrated circuit structure includes a semiconductor substrate including circuitry, a dielectric layer over the semiconductor substrate, an interconnect structure over the dielectric layer, and a first thermal fin extending through the semiconductor substrate, the dielectric layer, and the interconnect structure. The first thermal fin is electrically isolated from the circuitry. The thermal pillar is thermally coupled to the first thermal fin.

公开(公告)号：US11728217B2

公开(公告)日：2023-08-15

申请号：US17379775

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Mirng-Ji Lii ,  Chien-Hsun Lee ,  Jiun Yi Wu

IPC: H01L25/00 ,  H01L25/065 ,  H01L21/768 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L21/76898 ,  H01L21/568 ,  H01L24/19 ,  H01L25/105 ,  H01L25/50 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/73204 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2924/00012 ,  H01L2224/45144 ,  H01L2924/00 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2224/45147 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00012

Abstract: An embodiment is a package including a first package component. The first package component including a first die attached to a first side of a first interconnect structure, a molding material surrounding the first die, and a second interconnect structure over the molding material and the first die, a first side of the second interconnect structure coupled to the first die with first electrical connectors. The first package component further includes a plurality of through molding vias (TMVs) extending through the molding material, the plurality of TMVs coupling the first interconnect structure to the second interconnect structure, and a second die attached to a second side of the second interconnect structure with second electrical connectors, the second side of the second interconnect structure being opposite the first side of the second interconnect structure.