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公开(公告)号：US09847113B2
公开(公告)日：2017-12-19
申请号：US15258672
申请日：2016-09-07
发明人： Hun-dae Choi , Young-kwon Jo
CPC分类号： G11C7/222 , G11C7/1066 , G11C8/18 , G11C11/4076 , G11C11/4093 , G11C29/023 , H03K5/14 , H03K2005/00019 , H03L7/0812 , H03L7/0816
摘要： Provided is a delay-locked loop circuit for providing a delay-locked clock signal to a data output buffer, the delay-locked loop circuit including: a first delay-locked-mode-based selector configured to select, as a first selected clock signal, one of a first divided clock signal, which is obtained by dividing a reference clock signal by N, and the reference clock signal; and a delay-locked mode controller configured to determine a delay-locked mode on the basis of a command received from the outside and to control the first delay-locked-mode-based selector according to the delay-locked mode. The delay-locked clock signal is generated by comparing a phase of a feedback clock signal generated from the first selected clock signal with a phase of the reference clock signal.
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公开(公告)号：US09846606B2
公开(公告)日：2017-12-19
申请号：US14535335
申请日：2014-11-07
申请人： MEDIATEK INC.
发明人： Chun-Liang Chen
IPC分类号： G01R31/20 , G06F11/07 , G06F11/14 , G01R31/3185 , G01R1/04 , G01R31/265 , G06F11/22 , H04L1/00 , G06F11/00 , G11C11/00 , G11C29/00 , G01R31/28 , G01R31/04
CPC分类号： G06F11/0772 , G01R1/0466 , G01R1/0491 , G01R31/043 , G01R31/265 , G01R31/2868 , G01R31/2874 , G01R31/318511 , G06F11/00 , G06F11/0787 , G06F11/1492 , G06F11/22 , G11C11/00 , G11C29/00 , G11C29/023 , G11C29/028 , G11C29/44 , H04L1/00
摘要： A calibration method includes transmitting first data comprising a calibration data and a first checksum to the storage device according to each of a plurality of training parameter sets; recording a plurality of error indicators respectively which are corresponding to the plurality of training parameter sets and from the storage device; and identifying one of the plurality of training parameter sets as a predetermined parameter set according to the plurality of error indicators respectively corresponding to the plurality of training parameter sets; wherein each error indicator indicates whether transmitting the first data according to the corresponded training parameter set is successful.
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公开(公告)号：US20170352418A1
公开(公告)日：2017-12-07
申请号：US15676064
申请日：2017-08-14
申请人： Nantero, Inc.
发明人： Claude L. Bertin , Glen
CPC分类号： G11C13/0069 , B82Y10/00 , G11C7/14 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C13/0061 , G11C13/025 , G11C23/00 , G11C29/02 , G11C29/021 , G11C29/023 , G11C29/028 , G11C2013/0042 , G11C2013/0054 , G11C2213/35 , G11C2213/82 , H03K3/45 , H03K19/17728 , H03K19/17736 , H03K19/1776 , H03K19/1778 , H03K19/17796 , Y10S977/94
摘要： A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized data pulses. High speed data is received from an external synchronized data bus and stored by a PROGRAM operation within resistive change elements in a memory array configuration.
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公开(公告)号：US09824035B2
公开(公告)日：2017-11-21
申请号：US15426064
申请日：2017-02-07
申请人： Netlist, Inc.
发明人： Hyun Lee , Jayesh R. Bhakta
CPC分类号： G06F13/1673 , G06F1/10 , G06F3/0613 , G06F3/0647 , G06F3/0656 , G06F3/0659 , G06F3/0683 , G06F13/1642 , G06F13/28 , G06F13/4027 , G11C5/04 , G11C7/1006 , G11C7/1066 , G11C7/109 , G11C7/1093 , G11C7/20 , G11C8/12 , G11C8/18 , G11C16/00 , G11C29/023 , G11C29/028 , G11C2029/0407
摘要： A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device mounted on the module board to receive command signals from the memory controller and to output module command signals and module control signals, and memory devices mounted on the module board to perform a first memory operation in response to the module command signals. The memory module further comprises a plurality of buffer circuits distributed across a surface of the module board. Each respective buffer circuit is associated with a respective set of the memory devices and includes logic that is configured to obtain timing information based on signals received by the each respective buffer circuit during a second memory operation prior to the first memory operation and to control timing of the data and strobe signals through the each respective buffer circuit in accordance with the timing information.
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公开(公告)号：US20170330612A1
公开(公告)日：2017-11-16
申请号：US15667349
申请日：2017-08-02
发明人： Russel J. Baker
IPC分类号： G11C11/417
CPC分类号： G11C11/417 , G11C7/02 , G11C7/067 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C11/419 , G11C11/56 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/04 , G11C16/26 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2211/5634
摘要： A memory device that, in certain embodiments, includes a memory element coupled to a bit-line and a quantizing circuit coupled to the memory element via the bit-line. In some embodiments, the quantizing circuit includes an analog-to-digital converter having an input and output and a digital filter that includes memory. The input of the analog-to-digital converter may be coupled to the bit-line, and the output of the analog-to-digital converter may be coupled to the digital filter.
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公开(公告)号：US20170329535A1
公开(公告)日：2017-11-16
申请号：US15667130
申请日：2017-08-02
发明人： Young-Jin Jeon
IPC分类号： G06F3/06 , G11C11/4096 , G11C11/4093 , G11C11/4076 , G11C11/408
CPC分类号： G06F3/0614 , G06F3/0629 , G06F3/0659 , G06F3/0673 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/06 , G11C8/18 , G11C11/4076 , G11C11/4082 , G11C11/4087 , G11C11/409 , G11C11/4093 , G11C11/4096 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system.
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公开(公告)号：US09805773B1
公开(公告)日：2017-10-31
申请号：US15161908
申请日：2016-05-23
申请人： Intel Corporation
发明人： Dan Shi , Fangxing Wei , Michael J Allen
CPC分类号： G11C7/10 , G11C7/1072 , G11C7/222 , G11C29/023 , G11C29/028 , G11C2207/2254 , G11C2211/4061 , H03K5/05 , H03K5/1565
摘要： Examples may include techniques for dual-range clock duty cycle tuning of a clock signal used for an input/output data bus. A clock duty cycle of the clock signal is monitored to determine whether the clock duty cycle falls within a threshold of a 50 percent duty cycle. A dual-range tuning is then implemented until the clock duty cycle of the clock signal falls within the threshold.
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公开(公告)号：US09792969B1
公开(公告)日：2017-10-17
申请号：US15432214
申请日：2017-02-14
申请人： SK hynix Inc.
发明人： Hyun-Seung Kim , Kwang-Soon Kim , Seung-Wook Oh , Jin-Youp Cha
CPC分类号： G11C7/22 , G11C7/10 , G11C7/12 , G11C7/14 , G11C7/20 , G11C7/222 , G11C29/022 , G11C29/023 , G11C29/028
摘要： A semiconductor system includes a controller operatively coupled to a semiconductor device, the controller being suitable in a training mode for receiving an external signal and a first data signal from an external device and for transmitting the received external signal and the first data signal to the semiconductor device; and the semiconductor device being suitable in the training mode for determining a level of a reference voltage in response to the first data signal, and for transmitting a second data signal to the controller by buffering the external signal based on the reference voltage without performing a termination operation during an output period of the second data signal, wherein the controller controls an enable timing of the external signal by receiving the second data signal.
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公开(公告)号：US20170256302A1
公开(公告)日：2017-09-07
申请号：US15602662
申请日：2017-05-23
申请人： Maxlinear Inc.
发明人： Curtis Ling
IPC分类号： G11C11/406 , G11C11/404
CPC分类号： G11C11/406 , G11C11/404 , G11C11/40611 , G11C11/4076 , G11C29/023 , G11C29/028 , G11C29/42 , G11C29/50016 , G11C2029/0409 , G11C2029/0411 , G11C2207/104 , G11C2211/4062
摘要： An integrated circuit may comprise a digital logic circuit, a memory refresh circuit, and DRAM cells. A first portion of the DRAM cells may be refreshed by the memory refresh circuit. The DRAM cells store data received via a communication link and a rate at which the first portion of the DRAM cells is refreshed may be adjusted based on a symbol rate at which the data is received via the communication link. The DRAM cells may include one-transistor (“1T”) cells. The adjustment of the rate at which the first portion of the DRAM cells is refreshed may include an enabling of refresh of the first portion of the DRAM cells by the memory refresh circuit during a first time interval and a disabling of refresh of the first portion of the DRAM cells by the memory refresh circuit during a second time interval.
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公开(公告)号：US09742406B2
公开(公告)日：2017-08-22
申请号：US14737288
申请日：2015-06-11
申请人： Synopsys, Inc.
发明人： Jamil Kawa , Thu Nguyen , Raymond Tak-Hoi Leung
IPC分类号： H03K3/356 , H03K19/003
CPC分类号： H03K19/00384 , G11C5/14 , G11C8/08 , G11C11/417 , G11C29/023 , G11C29/028
摘要： A circuit skew compensation trigger system comprises a voltage divider including a P-transistor and an N-transistor and a center node in the voltage divider pulled to a first level. The circuit skew compensation trigger system further comprising a trigger to activate when a skew between the P-transistor and the N-transistor is above a threshold. The trigger to initiate a compensator to adjust for the skew.
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