公开(公告)号：US11848266B2

公开(公告)日：2023-12-19

申请号：US17467678

申请日：2021-09-07

申请人： SK hynix Inc.

发明人： Sung Lae Oh ,  Sang Woo Park ,  Dong Hyuk Chae

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H10B69/00

CPC分类号： H01L23/5226 ,  H01L21/76816 ,  H01L23/5283 ,  H10B69/00

摘要： A three-dimensional semiconductor device may comprise a first cell region, a second cell region, and a via plug region disposed between the first cell region and the second cell region; a word line stack disposed in the first cell region, the via plug region, and the second cell region, the word line stack including a plurality of word lines and a plurality of interlayer insulating layers which are alternately stacked; and a plurality of via plugs exclusively connected to the plurality of the word lines, respectively, by vertically penetrating through the word line stack in the via plug region. The via plugs may have an arrangement of a zigzag pattern in a row direction from a top view. The diameters of the via plugs may increase in the row direction.

公开(公告)号：US20230394214A1

公开(公告)日：2023-12-07

申请号：US18448117

申请日：2023-08-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chi-Hsiang WENG ,  Yu-Der CHIH

IPC分类号： G06F30/39 ,  G11C13/00 ,  H10B69/00 ,  H10B61/00 ,  H10B63/00

CPC分类号： G06F30/39 ,  G11C13/003 ,  H10B69/00 ,  H10B61/22 ,  H10B63/30 ,  H10B63/80 ,  G11C2213/79 ,  G06F30/392

摘要： A memory cell array includes a first and a second column of memory cells, a first and a second bit line, a source line and a first set of vias. The second bit line includes a first conductive line located on a first metal layer, and a second conductive line located on a second metal layer. The first and second conductive lines overlap a source of a transistor of a memory cell of the second column of memory cells. The source line is coupled to the first and second column of memory cells. The first set of vias is electrically coupled to the first and second conductive line. A pair of vias of the first set of vias is located above where the first conductive line overlaps each memory cell of the second column of memory cells.

公开(公告)号：US20230307553A1

公开(公告)日：2023-09-28

申请号：US18324638

申请日：2023-05-26

申请人： Samsung Electronics Co., Ltd.

发明人： Jinseong Heo ,  Taehwan Moon ,  Hagyoul Bae ,  Seunggeol Nam ,  Sangwook Kim ,  Kwanghee Lee

IPC分类号： H01L29/86 ,  H10K10/50 ,  H10K19/00 ,  H10B69/00

CPC分类号： H01L29/86 ,  H10K10/50 ,  H10K19/00 ,  H10K19/201 ,  H10B69/00

摘要： A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.

公开(公告)号：US20230282491A1

公开(公告)日：2023-09-07

申请号：US18113846

申请日：2023-02-24

申请人： Hitachi High-Tech Corporation

发明人： Naoyuki KOFUJI ,  Masahito MORI ,  Toshiaki NISHIDA ,  Ryoji HAMASAKI

IPC分类号： H01L21/67 ,  H01L21/3065 ,  H01J37/32 ,  H01L29/788 ,  H01L29/792 ,  H10B69/00 ,  H01L21/311

CPC分类号： H01L21/67069 ,  H01L21/3065 ,  H01J37/32183 ,  H01L29/788 ,  H01J37/3211 ,  H01J37/32357 ,  H01J37/321 ,  H01J37/32422 ,  H01L29/792 ,  H10B69/00 ,  H01J37/32192 ,  H01J37/32651 ,  H01J37/32678 ,  H01J37/32715 ,  H01L21/31116 ,  H10B41/20

摘要： Provided is a plasma processing apparatus capable of implementing both a radical irradiation step and an ion irradiation step using a single apparatus and controlling the ion irradiation energy from several tens eV to several KeV.
The plasma processing apparatus includes a mechanism (125, 126, 131, 132) for generating inductively coupled plasma, a perforated plate 116 for partitioning the vacuum processing chamber into upper and lower areas 106-1 and 106-2 and shielding ions, and a switch 133 for changing over between the upper and lower areas 106-1 and 106-2 as a plasma generation area.

公开(公告)号：US11751409B2

公开(公告)日：2023-09-05

申请号：US17466442

申请日：2021-09-03

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Tomoaki Atsumi ,  Shuhei Nagatsuka ,  Tamae Moriwaka ,  Yuta Endo

IPC分类号： H10B69/00 ,  H01L29/786 ,  H01L27/06 ,  G11C7/16 ,  G11C8/14 ,  G11C11/403 ,  G11C11/408 ,  H10B41/20 ,  H10B41/70 ,  G11C11/24 ,  H01L29/24

CPC分类号： H10B69/00 ,  G11C7/16 ,  G11C8/14 ,  G11C11/24 ,  G11C11/403 ,  G11C11/4085 ,  H01L27/0688 ,  H01L29/24 ,  H01L29/7869 ,  H10B41/20 ,  H10B41/70

摘要： To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j-lth sub memory cell.

公开(公告)号：US11705444B2

公开(公告)日：2023-07-18

申请号：US17342748

申请日：2021-06-09

申请人： KIOXIA CORPORATION

发明人： Hayato Masubuchi ,  Naoki Kimura ,  Manabu Matsumoto ,  Toyota Morimoto

IPC分类号： G11C5/02 ,  H01L25/18 ,  H05K1/02 ,  H05K3/30 ,  H10B69/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/552 ,  H01L23/00 ,  H01L25/065 ,  H05K1/18 ,  H01L23/528 ,  H01L25/00

CPC分类号： H01L25/18 ,  G11C5/02 ,  H01L23/3142 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5286 ,  H01L23/552 ,  H01L23/562 ,  H01L25/0655 ,  H01L25/50 ,  H05K1/0225 ,  H05K1/0271 ,  H05K1/0298 ,  H05K1/181 ,  H05K3/305 ,  H10B69/00 ,  H01L23/3121 ,  H01L2924/0002 ,  H05K2201/09136 ,  H05K2201/09681 ,  H05K2201/10159 ,  Y02P70/50 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.

公开(公告)号：US20230138802A1

公开(公告)日：2023-05-04

申请号：US18091432

申请日：2022-12-30

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Hideki UOCHI ,  Koichiro KAMATA

IPC分类号： G11C13/00 ,  G11C11/404 ,  H01L29/24 ,  H10B69/00 ,  H01L29/16 ,  H01L29/49

摘要： Disclosed is a semiconductor device having a memory cell which comprises a transistor having a control gate and a storage gate. The storage gate comprises an oxide semiconductor and is able to be a conductor and an insulator depending on the potential of the storage gate and the potential of the control gate. Data is written by setting the potential of the control gate to allow the storage gate to be a conductor, supplying a potential of data to be stored to the storage gate, and setting the potential of the control gate to allow the storage gate to be an insulator. Data is read by supplying a potential for reading to a read signal line connected to one of a source and a drain of the transistor and detecting the change in potential of a bit line connected to the other of the source and the drain.

公开(公告)号：US20240349517A1

公开(公告)日：2024-10-17

申请号：US18756056

申请日：2024-06-27

申请人： SK hynix Inc.

发明人： Ki Hong LEE

IPC分类号： H10B69/00 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50

CPC分类号： H10B69/00 ,  H01L23/5226 ,  H01L23/5283 ,  H01L28/00 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50

摘要： A semiconductor device may include a source layer, a stack structure, a channel layer, a slit, and a source pick-up line. The source layer may include at least one groove in an upper surface thereof. The stack structure may be formed over the source layer. The channel layer may pass through the stack structure. The channel layer may be in contact with the source layer. The slit may pass through the stack structure. The slit may expose the groove of the source layer therethrough. The source pick-up line may be formed in the slit and the groove. The source pick-up line may be contacted with the source layer.

公开(公告)号：US12100588B2

公开(公告)日：2024-09-24

申请号：US18214891

申请日：2023-06-27

申请人： ASM IP Holding B.V.

发明人： Toshiya Suzuki

IPC分类号： H01L21/02 ,  C23C16/40 ,  H01L21/3105 ,  H01L21/311 ,  H10B69/00 ,  C23C16/56

CPC分类号： H01L21/0234 ,  C23C16/402 ,  H01L21/02164 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3105 ,  H01L21/31111 ,  H10B69/00 ,  C23C16/401 ,  C23C16/56

摘要： A method of post-deposition treatment for silicon oxide film includes: providing in a reaction space a substrate having a recess pattern on which a silicon oxide film is deposited; supplying a reforming gas for reforming the silicon oxide film to the reaction space in the absence of a film-forming precursor, said reforming gas being composed primarily of He and/or H2; and irradiating the reforming gas with microwaves in the reaction space having a pressure of 200 Pa or less to generate a direct microwave plasma to which the substrate is exposed, thereby reforming the silicon oxide film.

公开(公告)号：US12094866B2

公开(公告)日：2024-09-17

申请号：US18203693

申请日：2023-05-31

申请人： Kioxia Corporation

发明人： Hayato Masubuchi ,  Naoki Kimura ,  Manabu Matsumoto ,  Toyota Morimoto

IPC分类号： G11C5/02 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/528 ,  H01L23/552 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H05K1/02 ,  H05K1/18 ,  H05K3/30 ,  H10B69/00

CPC分类号： H01L25/18 ,  G11C5/02 ,  H01L23/3142 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5286 ,  H01L23/552 ,  H01L23/562 ,  H01L25/0655 ,  H01L25/50 ,  H05K1/0225 ,  H05K1/0271 ,  H05K1/0298 ,  H05K1/181 ,  H05K3/305 ,  H10B69/00 ,  H01L23/3121 ,  H01L2924/0002 ,  H05K2201/09136 ,  H05K2201/09681 ,  H05K2201/10159 ,  Y02P70/50 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.