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    Proximity coupling interconnect packaging systems and methods
    52.
    发明授权
    Proximity coupling interconnect packaging systems and methods 有权

    公开(公告)号：US10381336B2

    公开(公告)日：2019-08-13

    申请号：US16046859

    申请日：2018-07-26

    Applicant: Micron Technology, Inc.

    Inventor： Rich Fogal ,  Owen R. Fay

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/02 ,  H01L21/00 ,  H01L25/00 ,  H01L25/18 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/54 ,  H01L23/522

    Abstract: Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.

    INTERCONNECT STRUCTURES FOR PREVENTING SOLDER BRIDGING, AND ASSOCIATED SYSTEMS AND METHODS
    53.
    发明申请
    INTERCONNECT STRUCTURES FOR PREVENTING SOLDER BRIDGING, AND ASSOCIATED SYSTEMS AND METHODS 审中-公开

    公开(公告)号：US20190198470A1

    公开(公告)日：2019-06-27

    申请号：US16182924

    申请日：2018-11-07

    Applicant: Micron Technology, Inc.

    Inventor： Kyle S. Mayer ,  Owen R. Fay

    IPC: H01L23/00 ,  H01L21/288

    Abstract: Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process.

    Proximity coupling of interconnect packaging systems and methods
    54.
    发明授权
    Proximity coupling of interconnect packaging systems and methods 有权

    公开(公告)号：US10062678B2

    公开(公告)日：2018-08-28

    申请号：US15422230

    申请日：2017-02-01

    Applicant: Micron Technology, Inc.

    Inventor： Rich Fogal ,  Owen R. Fay

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/02 ,  H01L21/00 ,  H01L25/00 ,  H01L21/48 ,  H01L21/54 ,  H01L23/00 ,  H01L25/065 ,  H01L23/522

    Abstract: Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.

    USE OF PRE-CHANNELED MATERIALS FOR ANISOTROPIC CONDUCTORS
    59.
    发明申请
    USE OF PRE-CHANNELED MATERIALS FOR ANISOTROPIC CONDUCTORS 有权

    公开(公告)号：US20240387441A1

    公开(公告)日：2024-11-21

    申请号：US18787347

    申请日：2024-07-29

    Applicant: Micron Technology, Inc.

    Inventor： Mark E. Tuttle ,  John F. Kaeding ,  Owen R. Fay ,  Eiichi Nakano ,  Shijian Luo

    IPC: H01L23/00

    Abstract: A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate. The method may include passing electrical current through the plurality of interconnects.

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