公开(公告)号：US20170170363A1

公开(公告)日：2017-06-15

申请号：US15377775

申请日：2016-12-13

Applicant: Ostendo Technologies, Inc.

Inventor： Anna Volkova ,  Vladimir Ivantsov ,  Alexander Syrkin ,  Benjamin A. Haskell ,  Hussein S. El-Ghoroury

IPC: H01L33/24 ,  H01L33/32 ,  H01L33/18 ,  H01L33/08 ,  H01L27/15 ,  H01J1/308 ,  H01L31/0304 ,  H01L31/0352 ,  H01L31/036 ,  H01L31/109 ,  H01L31/18 ,  H01L33/00 ,  H01L33/06

CPC classification number: H01J1/308 ,  C30B29/406 ,  C30B29/607 ,  C30B29/62 ,  C30B29/66 ,  H01L21/0254 ,  H01L21/02603 ,  H01L21/20 ,  H01L31/035236 ,  H01L31/035281 ,  H01L31/109 ,  H01L31/1848 ,  H01L31/1852 ,  H01L33/007 ,  H01L33/06 ,  H01L33/08 ,  H01L33/18 ,  H01L33/24 ,  H01L33/32 ,  Y02E10/544

Abstract: A method for growing on a substrate strongly aligned uniform cross-section semiconductor composite nanocolumns is disclosed. The method includes: (a) forming faceted pyramidal pits on the substrate surface; (b) initiating nucleation on the facets of the pits; and; (c) promoting the growth of nuclei toward the center of the pits where they coalesce with twinning and grow afterwards together as composite nanocolumns. Multi-quantum-well, core-shell nanocolumn heterostructures can be grown on the sidewalls of the nanocolumns. Furthermore, a continuous semiconductor epitaxial layer can be formed through the overgrowth of the nanocolumns to facilitate fabrication of high-quality planar device structures or for light emitting structures.

公开(公告)号：US09680041B2

公开(公告)日：2017-06-13

申请号：US14578161

申请日：2014-12-19

Applicant: Solexel, Inc.

Inventor： Mehrdad M. Moslehi ,  David Xuan-Qi Wang

IPC: H01L31/00 ,  H01L31/0352 ,  H01L31/18 ,  H01L31/0468 ,  H01L27/142 ,  H01L31/0224 ,  H01L31/054 ,  H01L31/056

CPC classification number: H01L31/0352 ,  H01L21/00 ,  H01L27/142 ,  H01L31/022458 ,  H01L31/035281 ,  H01L31/03529 ,  H01L31/0468 ,  H01L31/054 ,  H01L31/056 ,  H01L31/1804 ,  H01L31/1892 ,  Y02E10/547 ,  Y02P70/521

Abstract: A three-dimensional thin-film semiconductor substrate with selective through-holes is provided. The substrate having an inverted pyramidal structure comprising selectively formed through-holes positioned between the front and back lateral surface planes of the semiconductor substrate to form a partially transparent three-dimensional thin-film semiconductor substrate.

公开(公告)号：US09679091B2

公开(公告)日：2017-06-13

申请号：US13745338

申请日：2013-01-18

Applicant: U.S. Army Research Laboratory

Inventor： Kwong-Kit Choi

IPC: G06F17/50 ,  B82Y20/00 ,  H01L31/0232 ,  H01L27/146 ,  H01L31/0352 ,  H01L31/09 ,  H01L27/144

CPC classification number: G06F17/5045 ,  B82Y20/00 ,  H01L27/1446 ,  H01L27/14601 ,  H01L27/14603 ,  H01L27/14683 ,  H01L31/0232 ,  H01L31/02327 ,  H01L31/02966 ,  H01L31/035236 ,  H01L31/035281 ,  H01L31/09 ,  Y02E10/50

Abstract: A method for designing a photodetector comprising an array of pixels: selecting at a material composition for the photodetector; determining a configuration of at least one pixel in the array of pixels using a computer simulation, each pixel comprising an active region and a diffractive region, and a photodetector/air interface through which light enters, the computer simulation operating to process different configurations of the pixel to determine an optimal configuration for a predetermined wavelength or wavelength range occurring when waves reflected by the diffractive element form a constructive interference pattern inside the active region to thereby increase the quantum efficiency of the photodetector. An infrared photodetector produced by the method.

公开(公告)号：US09666744B2

公开(公告)日：2017-05-30

申请号：US13832095

申请日：2013-03-15

Applicant: Russ Clements

Inventor： Russ Clements

IPC: F21V7/04 ,  H01L31/18 ,  H01L31/0352 ,  F21V8/00 ,  F21S8/04 ,  F21V7/00 ,  F21V17/16 ,  F21Y115/10

CPC classification number: G02B6/0075 ,  F21S8/04 ,  F21V7/0008 ,  F21V17/16 ,  F21Y2115/10 ,  G02B6/0011 ,  G02B6/0046 ,  G02B6/0055 ,  G02B6/0068 ,  G02B6/0073 ,  G02B6/0083 ,  G02B6/0088 ,  G02B6/0091 ,  G02B6/0095 ,  H01L31/035281 ,  H01L31/18

Abstract: A lighting system can include a lightguide having an edge and two major surfaces. The lightguide can be mounted in a frame so that one of the major surfaces faces towards an area to be illuminated, while the other major surface faces away from the area. LEDs can couple light into the lightguide edge, with the coupled light emitting from both major surfaces. Light emitted from the major surface that faces away from the area to be illuminated can be reflected back into the lightguide by a reflective surface. The reflective surface can be separated from the lightguide by an air gap. The air gap can promote internal reflection at the major surface facing away from the area to be illuminated, thereby enhancing homogeneity and output of light towards the area to be illuminated. The frame can include integral wireways, reflector retention clips, and grounding circuitry.

公开(公告)号：US20170133524A1

公开(公告)日：2017-05-11

申请号：US15406125

申请日：2017-01-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Solomon Assefa ,  Bruce W. Porth ,  Steven M. Shank

IPC: H01L31/0232 ,  G02B6/122 ,  H01L31/18 ,  G02B6/13 ,  H01L31/0203 ,  H01L31/09

CPC classification number: H01L31/208 ,  G02B6/12004 ,  G02B6/1228 ,  G02B6/13 ,  G02B6/136 ,  G02B6/42 ,  G02B6/4203 ,  G02B6/4295 ,  G02B2006/12061 ,  G02B2006/12123 ,  G06F17/5045 ,  H01L29/0649 ,  H01L31/0203 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/0304 ,  H01L31/035281 ,  H01L31/09 ,  H01L31/1804 ,  H01L31/1808 ,  H01L31/182 ,  H01L31/184 ,  H01L31/1864 ,  H01L31/1872 ,  Y02E10/544 ,  Y02P70/521

Abstract: An encapsulated integrated photodetector waveguide structures with alignment tolerance and methods of manufacture are disclosed. The method includes forming a waveguide structure bounded by one or more shallow trench isolation (STI) structure(s). The method further includes forming a photodetector fully landed on the waveguide structure.

公开(公告)号：US20170133523A1

公开(公告)日：2017-05-11

申请号：US14936900

申请日：2015-11-10

Applicant: International Business Machines Corporation

Inventor： Bahman Hekmatshoartabari ,  Ning Li ,  Katherine L. Saenger

IPC: H01L31/0216 ,  H01L31/18 ,  H01L31/028 ,  H01L31/0224 ,  H01L31/075

CPC classification number: H01L31/1868 ,  H01L31/02167 ,  H01L31/022425 ,  H01L31/022441 ,  H01L31/028 ,  H01L31/035281 ,  H01L31/03529 ,  H01L31/03921 ,  H01L31/0445 ,  H01L31/068 ,  H01L31/0745 ,  H01L31/075 ,  H01L31/1804 ,  H01L31/186 ,  H02S50/10 ,  Y02E10/547

Abstract: After forming an absorber layer containing cracks over a back contact layer, a passivation layer is formed over a top surface of the absorber layer and interior surfaces of the cracks. The passivation layer is deposited in a manner such that that the cracks in the absorber layer are fully passivated by the passivation layer. An emitter layer is then formed over the passivation layer to pinch off upper portions of the cracks, leaving voids in lower portions of the cracks.

公开(公告)号：US09640703B2

公开(公告)日：2017-05-02

申请号：US11666091

申请日：2004-10-25

Applicant: Eiji Yagyu ,  Eitaro Ishimura ,  Masaharu Nakaji

Inventor： Eiji Yagyu ,  Eitaro Ishimura ,  Masaharu Nakaji

IPC: H01L31/107 ,  H01L31/0352

CPC classification number: H01L31/1075 ,  H01L31/035281 ,  H01L31/03529 ,  Y02E10/50

Abstract: In an avalanche photodiode provided with a substrate including a first electrode and a first semiconductor layer, formed of a first conductivity type, which is connected to the first electrode, the configuration is in such a way that, at least an avalanche multiplication layer, a light absorption layer, and a second semiconductor layer having a bandgap that is larger than that of the light absorption layer are layered on the substrate; a second conductivity type conductive region is formed in the second semiconductor layer; and the second conductivity type conductive region is arranged so as to be connected to a second electrode. With the foregoing configuration, an avalanche photodiode having a small dark current and a high long-term reliability can be provided with a simple process.Additionally, the configuration is in such a way that, by removing at least the light absorption layer among the layers which are layered on the peripheral portion, of the substrate, on which the second conductivity type conductive region and the second semiconductor layer around the second conductivity type conductive region are surrounded by that layers, a side face of the light absorption layer is formed. With the configuration, the dark current can be further reduced.

公开(公告)号：US09640684B2

公开(公告)日：2017-05-02

申请号：US15210423

申请日：2016-07-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Solomon Assefa ,  Bruce W. Porth ,  Steven M. Shank

IPC: H01L31/18 ,  H01L31/0232 ,  G02B6/12 ,  G02B6/122 ,  H01L31/0203 ,  H01L31/028 ,  H01L31/0304 ,  H01L31/09

CPC classification number: H01L31/208 ,  G02B6/12004 ,  G02B6/1228 ,  G02B6/13 ,  G02B6/136 ,  G02B6/42 ,  G02B6/4203 ,  G02B6/4295 ,  G02B2006/12061 ,  G02B2006/12123 ,  G06F17/5045 ,  H01L29/0649 ,  H01L31/0203 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/0304 ,  H01L31/035281 ,  H01L31/09 ,  H01L31/1804 ,  H01L31/1808 ,  H01L31/182 ,  H01L31/184 ,  H01L31/1864 ,  H01L31/1872 ,  Y02E10/544 ,  Y02P70/521

Abstract: An encapsulated integrated photodetector waveguide structures with alignment tolerance and methods of manufacture are disclosed. The method includes forming a waveguide structure bounded by one or more shallow trench isolation (STI) structure(s). The method further includes forming a photodetector fully landed on the waveguide structure.

公开(公告)号：US20170114444A1

公开(公告)日：2017-04-27

申请号：US15318330

申请日：2015-06-11

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Martin LEMBERGER ,  Michael SCHMAL ,  Julian IKONOMOV

IPC: C23C14/22 ,  H01L33/46 ,  H01L31/0352 ,  H01L31/0232 ,  H01L31/0224 ,  H01L33/20 ,  C23C14/50 ,  H01L33/38

CPC classification number: C23C14/225 ,  C23C14/505 ,  H01L31/022408 ,  H01L31/02327 ,  H01L31/035281 ,  H01L33/20 ,  H01L33/38 ,  H01L33/46 ,  H01L2933/0025

Abstract: What is specified is a method for producing a coating comprising the following steps:—providing a material source having a top surface and a main coating direction,—providing a substrate holder having a top surface,—providing at least one base layer, having a coating surface remote from the substrate holder, on the top surface of the substrate,—attaching the substrate holder to a rotating arm, which has a length along a main direction of extent of the rotating arm,—setting the length of the rotating arm in such a manner that a normal angle (φ) throughout the method is at least 30° and at most 75°,—applying at least one coating to that side of the base layer which has the coating surface by means of the material source, wherein—during the coating process with the coating, the substrate holder is rotated about a substrate axis of rotation running along the main direction of extent of the rotating arm.

公开(公告)号：US09608149B2

公开(公告)日：2017-03-28

申请号：US12998898

申请日：2008-12-19

Applicant: Josuke Nakata

Inventor： Josuke Nakata

IPC: H01L31/05 ,  H01L31/0352 ,  H01L31/02 ,  H01L31/048

CPC classification number: H01L31/03529 ,  H01L31/02 ,  H01L31/035281 ,  H01L31/044 ,  H01L31/0488 ,  H01L31/0508 ,  Y02E10/50

Abstract: This solar cell module (1) comprises a plurality of solar cell arrays (11). Each solar cell array (11) includes a plurality of spherical semiconductor elements (20) arranged in a row, at least a pair of bypass diodes (40), and a pair of lead members (14) that connect the plurality of spherical semiconductor elements (20) and the plurality of bypass diodes (40) in parallel. Each of the lead members (14) includes one or plural lead strings (15) to which the plurality of spherical semiconductor elements (20) are electrically connected and having a width less than or equal to the radius of the spherical semiconductor element (20), and plural lead pieces (16) formed integrally with the lead strings (15) at least at both end portions of the lead member (14), on which the bypass diodes (40) are electrically connected in reverse parallel to the spherical semiconductor elements (20), and having width larger than or equal to the width of the bypass diodes (40).