公开(公告)号：US20130020704A1

公开(公告)日：2013-01-24

申请号：US13185044

申请日：2011-07-18

Applicant: Mariam Sadaka

Inventor： Mariam Sadaka

IPC: H01L23/48 ,  H01L21/762 ,  H01L21/30

CPC classification number: H01L24/80 ,  H01L23/3178 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03616 ,  H01L2224/03831 ,  H01L2224/03845 ,  H01L2224/0391 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/80097 ,  H01L2224/80357 ,  H01L2224/80365 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80986 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/20105 ,  H01L2224/05552

Abstract: Methods of directly bonding a first semiconductor structure to a second semiconductor structure include directly bonding at least one device structure of a first semiconductor structure to at least one device structure of a second semiconductor structure in a conductive material-to-conductive material direct bonding process. In some embodiments, at least one device structure of the first semiconductor structure may be caused to project a distance beyond an adjacent dielectric material on the first semiconductor structure prior to the bonding process. In some embodiments, one or more of the device structures may include a plurality of integral protrusions that extend from a base structure. Bonded semiconductor structures are fabricated using such methods.

Abstract translation: 将第一半导体结构直接接合到第二半导体结构的方法包括在导电材料 - 导电材料直接接合工艺中将至少一个第一半导体结构的器件结构直接结合到第二半导体结构的至少一个器件结构。 在一些实施例中，在接合过程之前，可以使第一半导体结构的至少一个器件结构在第一半导体结构上突出超过相邻电介质材料的距离。 在一些实施例中，一个或多个装置结构可以包括从基部结构延伸的多个整体突起。 使用这种方法制造粘合的半导体结构。

公开(公告)号：US20120248621A1

公开(公告)日：2012-10-04

申请号：US13077292

申请日：2011-03-31

Applicant: Mariam Sadaka

Inventor： Mariam Sadaka

IPC: H01L21/302 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/80 ,  H01L24/92 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2224/03002 ,  H01L2224/033 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05571 ,  H01L2224/08145 ,  H01L2224/0903 ,  H01L2224/09051 ,  H01L2224/09519 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/80203 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80986 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00012 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2224/03 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014

Abstract: Methods of forming bonded semiconductor structures include providing a first semiconductor structure including a device structure, bonding a second semiconductor structure to the first semiconductor structure below about 400° C., forming a through wafer interconnect through the second semiconductor structure and into the first semiconductor structure, and bonding a third semiconductor structure to the second semiconductor structure on a side thereof opposite the first semiconductor structure. In additional embodiments, a first semiconductor structure is provided. Ions are implanted into a second semiconductor structure. The second semiconductor structure is bonded to the first semiconductor structure. The second semiconductor structure is fractured along an ion implant plane, a through wafer interconnect is formed at least partially through the first and second semiconductor structures, and a third semiconductor structure is bonded to the second semiconductor structure on a side thereof opposite the first semiconductor structure. Bonded semiconductor structures are formed using such methods.

Abstract translation: 形成键合的半导体结构的方法包括提供包括器件结构的第一半导体结构，将第二半导体结构键合到低于约400℃的第一半导体结构，形成通过第二半导体结构的贯穿晶片互连并进入第一半导体结构 并且在与第一半导体结构相对的一侧上将第三半导体结构接合到第二半导体结构。 在另外的实施例中，提供了第一半导体结构。 离子植入第二半导体结构。 第二半导体结构被结合到第一半导体结构。 第二半导体结构沿着离子注入平面断裂，至少部分地穿过第一和第二半导体结构形成贯通晶片互连，并且第三半导体结构在与第一半导体结构相对的一侧上结合到第二半导体结构 。 使用这种方法形成结合的半导体结构。

公开(公告)号：US20120190170A1

公开(公告)日：2012-07-26

申请号：US13409888

申请日：2012-03-01

Applicant: Oleg Kononchuk

Inventor： Oleg Kononchuk

IPC: H01L21/762

CPC classification number: H01L21/7624

Abstract: A method for dissolving the buried oxide layer of a SeOI wafer in order to decrease its thickness. The SeOI wafer includes a thin working layer made from one or more semiconductor material(s); a support layer, and a buried oxide (BOX) layer between the working layer and the support layer. The dissolution rate of the buried oxide layer is controlled and set to be below 0.06 Å/sec.

Abstract translation: 一种用于溶解SeOI晶片的掩埋氧化物层以减小其厚度的方法。 SeOI晶片包括由一种或多种半导体材料制成的薄工作层; 支撑层和工作层和支撑层之间的掩埋氧化物（BOX）层。 掩埋氧化物层的溶解速度被控制并设定为低于0.06埃/秒。

公开(公告)号：US20120153484A1

公开(公告)日：2012-06-21

申请号：US12970422

申请日：2010-12-16

Applicant: Mariam Sadaka

Inventor： Mariam Sadaka

IPC: H01L23/532 ,  H01L21/60

CPC classification number: H01L21/76849 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76883 ,  H01L21/76886 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0239 ,  H01L2224/03444 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0381 ,  H01L2224/0384 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05186 ,  H01L2224/05187 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05638 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05687 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/08501 ,  H01L2224/0903 ,  H01L2224/80121 ,  H01L2224/802 ,  H01L2224/80203 ,  H01L2224/80357 ,  H01L2224/80894 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2924/01014 ,  H01L2924/0509 ,  H01L2224/05157 ,  H01L2924/0105 ,  H01L2924/01015 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01025 ,  H01L2924/05042 ,  H01L2924/04642 ,  H01L2924/05442 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Embodiments of the present invention include methods of directly bonding together semiconductor structures. In some embodiments, a cap layer may be provided at an interface between directly bonded metal features of the semiconductor structures. In some embodiments, impurities are provided within the directly bonded metal features of the semiconductor structures. Bonded semiconductor structures are formed using such methods.

Abstract translation: 本发明的实施例包括将半导体结构直接结合在一起的方法。 在一些实施例中，盖层可以设置在半导体结构的直接结合的金属特征之间的界面处。 在一些实施例中，在半导体结构的直接结合的金属特征内提供杂质。 使用这种方法形成结合的半导体结构。

公开(公告)号：US08093686B2

公开(公告)日：2012-01-10

申请号：US12672819

申请日：2008-09-01

Applicant: Arnaud Garnier

Inventor： Arnaud Garnier

IPC: H01L29/20

CPC classification number: H01L21/76254 ,  H01L33/0079

Abstract: A process for obtaining a hybrid substrate that includes at least one active layer of Group III/N material for applications in the field of electronics, optics, photovoltaics or optoelectronics. The method includes selecting a source substrate of Group III/N material having a hexagonal single crystal crystallographic structure; carrying out an implantation of He+ helium ions into the source substrate through an implantation face which lies in a plane approximately parallel with the “c” crystallographic axis of the material, at an implantation dose equal to or greater than 1×1016 He+/cm2 and 1×1017 He+/cm2, to form therein a number of nanocavities defining a weakened zone which delimits the active layer; and transferring the active layer by applying an overall energy budget capable of causing detachment of the layer from the source substrate, wherein the budget also causes the nanocavities to grow into cavities.

Abstract translation: 一种用于获得混合基板的方法，该混合基板包括用于电子，光学，光伏或光电领域领域的III / N族材料的至少一个有源层。 该方法包括选择具有六方晶单晶晶体结构的III / N族材料的源极衬底; 通过位于与材料的“c”结晶轴大致平行的平面中的注入面，以等于或大于1×10 16 He + / cm 2的注入剂量，将He +氦离子注入到源衬底中，并且 1×1017 He + / cm 2，以在其中形成限定限定活性层的弱化区的许多纳米孔; 并且通过施加能够使得所述层与所述源极基板分离的总能量预算来转移所述有源层，其中所述预算还导致所述纳米空间生长到空腔中。

公开(公告)号：US08067298B2

公开(公告)日：2011-11-29

申请号：US12574142

申请日：2009-10-06

Applicant: Oleg Kononchuk

Inventor： Oleg Kononchuk

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L21/187 ,  H01L21/02422 ,  H01L21/02488 ,  H01L21/0254 ,  H01L21/02667

Abstract: The invention relates to methods of fabricating a layer of at least partially relaxed material, such as for electronics, optoelectronics or photovoltaics. An exemplary method includes supplying a structure that includes a layer of strained material situated between a reflow layer and a stiffener layer. The method further includes applying a heat treatment that brings the reflow layer to a temperature equal to or greater than the glass transition temperature of the reflow layer, and the thickness of the stiffener layer is progressively reduced during heat treatment. The invention also relates to an exemplary method of fabricating semiconductor devices on a layer of at least partially relaxed material. Specifically, at least one active layer may be formed on the at least partially relaxed material layer. The active layer may include laser components, photovoltaic components and/or electroluminescent diodes.

Abstract translation: 本发明涉及制造至少部分松弛的材料的层的方法，例如用于电子学，光电子学或光电子学。 示例性方法包括提供包括位于回流层和加强层之间的应变材料层的结构。 该方法还包括应用使回流层达到等于或大于回流层的玻璃化转变温度的温度的热处理，并且加热层的厚度在热处理期间逐渐降低。 本发明还涉及在至少部分松弛的材料层上制造半导体器件的示例性方法。 具体地说，可以在至少部分松弛的材料层上形成至少一个活性层。 有源层可以包括激光组件，光伏组件和/或电致发光二极管。

公开(公告)号：US20110284863A1

公开(公告)日：2011-11-24

申请号：US13069900

申请日：2011-03-23

Applicant: Ed Lindow ,  Chantal Arena ,  Ronald Bertram ,  Ranjan Datta ,  Subhash Mahajan

Inventor： Ed Lindow ,  Chantal Arena ,  Ronald Bertram ,  Ranjan Datta ,  Subhash Mahajan

IPC: H01L29/20 ,  H01L21/20

CPC classification number: H01L29/2003 ,  H01L21/0237 ,  H01L21/02455 ,  H01L21/02458 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02617 ,  H01L21/0262

Abstract: Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation.

Abstract translation: 本发明的实施例涉及制造半导体结构的方法以及通过这些方法制造的半导体结构。 在一些实施例中，该方法可用于制造诸如InGaN的III-V材料的半导体结构。 通过使用不同的生长条件生长子层来制造半导体层，以改善所得层的均匀性，改善所得层的表面粗糙度和/或使层能够生长到增加的厚度而不发生 的应变松弛。

公开(公告)号：US20110266651A1

公开(公告)日：2011-11-03

申请号：US13143170

申请日：2010-02-11

Applicant: Gregory Riou ,  Didier Landru

Inventor： Gregory Riou ,  Didier Landru

IPC: H01L21/762 ,  H01L27/04

CPC classification number: H01L21/76264 ,  H01L21/76243

Abstract: The invention relates to a method for manufacturing components on a mixed substrate. It comprises the following steps: —providing a substrate of the semiconductor-on-insulator (SeOI) type comprising a buried oxide layer between a supporting substrate and a thin layer, —forming in this substrate a plurality of trenches opening out at the free surface of the thin layer and extending over a depth such that it passes through the thin layer and the buried oxide layer, these primary trenches delimiting at least one island of the SeOI substrate, —forming a mask inside the primary trenches and as a layer covering the areas of the free surface of the thin layer located outside the islands, —proceeding with heat treatment for dissolving the buried oxide layer present at the island, so as to reduce the thickness thereof.

Abstract translation: 本发明涉及一种在混合基板上制造部件的方法。 它包括以下步骤： - 在支撑衬底和薄层之间提供包括掩埋氧化物层的绝缘体上半导体（SeOI）类型的衬底，在该衬底中形成多个在自由表面处开口的沟槽 并且延伸穿过薄层和掩埋氧化物层的深度，这些初级沟槽限定了至少一个SeOI衬底的岛，形成了主沟槽内的掩模，并且覆盖了覆盖层 位于岛外的薄层的自由表面的区域，通过用于溶解存在于岛上的掩埋氧化物层的热处理，以减小其厚度。

公开(公告)号：US08049224B2

公开(公告)日：2011-11-01

申请号：US12862471

申请日：2010-08-24

Applicant: Bruno Ghyselen ,  Daniel Bensahel ,  Thomas Skotnicki

Inventor： Bruno Ghyselen ,  Daniel Bensahel ,  Thomas Skotnicki

IPC: H01L29/12

CPC classification number: H01L29/1054 ,  H01L21/76254 ,  H01L21/76259 ,  Y10S438/938

Abstract: Semiconductor wafers having a thin layer of strained semiconductor material. These structures include a substrate; an oxide layer upon the substrate; a silicon carbide (SiC) layer upon the oxide layer, and a strained layer of a semiconductor material in a strained state upon the silicon carbide layer, or a matching layer upon the donor substrate that is made from a material that induces strain in subsequent epitaxially grown layers thereon; a strained layer of a semiconductor material of defined thickness in a strained state; and an insulating or semi-insulating layer upon the strained layer in a thickness that retains the strained state of the strained layer. The insulating or semi-insulating layers are made of silicon carbide or oxides and act to retain strain in the strained layer.

Abstract translation: 半导体晶片具有应变半导体材料的薄层。 这些结构包括底物; 基底上的氧化物层; 氧化物层上的碳化硅（SiC）层，以及在碳化硅层上处于应变状态的半导体材料的应变层，或者由施主衬底上的由随后的外延生长引起应变的材料制成的匹配层 生长层; 在应变状态下具有规定厚度的半导体材料的应变层; 以及在应变层上的绝缘或半绝缘层，其厚度保持应变层的应变状态。 绝缘层或半绝缘层由碳化硅或氧化物制成并用于将应变保留在应变层中。

公开(公告)号：US08035163B2

公开(公告)日：2011-10-11

申请号：US12470253

申请日：2009-05-21

Applicant: Bich-Yen Nguyen ,  Carlos Mazure

Inventor： Bich-Yen Nguyen ,  Carlos Mazure

IPC: H01L29/66 ,  H01L21/30 ,  H01L21/46

CPC classification number: H01L21/76254 ,  H01L21/76256

Abstract: In preferred embodiments, the invention provides substrates that include a support, a first insulating layer arranged on the support, a non-mono-crystalline semi-conducting layer arranged on the first insulating layer, a second insulating layer arranged on the non-mono-crystalline semi-conducting layer; and top layer disposed on the second insulating layer. Additionally, a first gate electrode can be formed on the top layer and a second gate electrode can be formed in the non-mono-crystalline semi-conducting layer. The invention also provides methods for manufacture of such substrates.

Abstract translation: 在优选实施例中，本发明提供了包括支撑件，布置在支撑件上的第一绝缘层，布置在第一绝缘层上的非单晶半导体层的衬底，布置在非单晶半导体层上的第二绝缘层， 结晶半导体层; 以及设置在第二绝缘层上的顶层。 此外，可以在顶层上形成第一栅电极，并且可以在非单晶半导体层中形成第二栅电极。 本发明还提供了制造这种基材的方法。