公开(公告)号：US20230253361A1

公开(公告)日：2023-08-10

申请号：US17669236

申请日：2022-02-10

申请人： Tokyo Electron Limited

发明人： Jack Rogers ,  Satohiko Hoshino ,  Nathan Antonovich

IPC分类号： H01L23/00

CPC分类号： H01L24/80 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2224/80013 ,  H01L2224/8002 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/0509

摘要： Technologies for plasma oxidation protection during hybrid bonding of semiconductor devices includes forming a blocking layer on a metallic bonding pad formed in a bonding surface of a semiconductor device to be bonded and performing a surface treatment on the bonding surface to increase the bonding strength of the bonding surface and contemporaneously remove the blocking layer from the metallic bonding pad. In an illustrative embodiment, the blocking layer is embodied as a self-assembled monolayer (SAM), and the surface treatment is embodied as a surface activation plasma (SAP) treatment. A diffusion barrier layer, such as a silicon carbon nitride layer, may form the bonding surface in some embodiments to reduce diffusion of the metallic bonding pad during an annealing treatment of the bonding process.

公开(公告)号：US20120153484A1

公开(公告)日：2012-06-21

申请号：US12970422

申请日：2010-12-16

申请人： Mariam Sadaka

发明人： Mariam Sadaka

IPC分类号： H01L23/532 ,  H01L21/60

CPC分类号： H01L21/76849 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76883 ,  H01L21/76886 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0239 ,  H01L2224/03444 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0381 ,  H01L2224/0384 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05186 ,  H01L2224/05187 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05638 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05687 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/08501 ,  H01L2224/0903 ,  H01L2224/80121 ,  H01L2224/802 ,  H01L2224/80203 ,  H01L2224/80357 ,  H01L2224/80894 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2924/01014 ,  H01L2924/0509 ,  H01L2224/05157 ,  H01L2924/0105 ,  H01L2924/01015 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01025 ,  H01L2924/05042 ,  H01L2924/04642 ,  H01L2924/05442 ,  H01L2224/05552 ,  H01L2924/00

摘要： Embodiments of the present invention include methods of directly bonding together semiconductor structures. In some embodiments, a cap layer may be provided at an interface between directly bonded metal features of the semiconductor structures. In some embodiments, impurities are provided within the directly bonded metal features of the semiconductor structures. Bonded semiconductor structures are formed using such methods.

摘要翻译： 本发明的实施例包括将半导体结构直接结合在一起的方法。 在一些实施例中，盖层可以设置在半导体结构的直接结合的金属特征之间的界面处。 在一些实施例中，在半导体结构的直接结合的金属特征内提供杂质。 使用这种方法形成结合的半导体结构。

公开(公告)号：US20230299023A1

公开(公告)日：2023-09-21

申请号：US17698545

申请日：2022-03-18

申请人： NANYA TECHNOLOGY CORPORATION

发明人： TENG-YEN HUANG

IPC分类号： H01L23/00 ,  H01L25/065

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/80 ,  H01L24/06 ,  H01L24/08 ,  H01L25/0657 ,  H01L24/02 ,  H01L2224/02372 ,  H01L2224/03001 ,  H01L2224/03011 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03452 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05018 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2924/04941 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2924/0496 ,  H01L2924/0509 ,  H01L2924/04953 ,  H01L2224/05193 ,  H01L2224/05559 ,  H01L2224/05546 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05684 ,  H01L2224/05676 ,  H01L2224/0568 ,  H01L2224/06181 ,  H01L2224/06051 ,  H01L2224/0603 ,  H01L2224/06517 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/80379 ,  H01L2924/0544 ,  H01L2924/0504 ,  H01L2924/059 ,  H01L2924/30105

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure and a first connecting structure, wherein the first connecting structure includes a first connecting insulating layer positioned on the first semiconductor structure, two first conductive layers positioned in the first connecting insulating layer, and a first porous layer positioned between the two first conductive layers. A porosity of the first porous layer is between about 25% and about 100%. The first semiconductor structure includes a plurality of first composite conductive features, wherein at least one of the plurality of first composite conductive features includes a first protection liner, a first graphene liner in the first protection liner and a first core conductor in the first graphene liner.

公开(公告)号：US20170248590A1

公开(公告)日：2017-08-31

申请号：US15097899

申请日：2016-04-13

申请人： National Tsing Hua University

发明人： Yu-Lin Wang ,  Chen-Pin Hsu ,  Pei-Chi Chen

IPC分类号： G01N33/543 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48

CPC分类号： H01L24/32 ,  G01D11/245 ,  H01L21/4846 ,  H01L21/565 ,  H01L23/3107 ,  H01L2224/32225 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/0496 ,  H01L2924/0509 ,  H01L2924/06 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/1082 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/1306 ,  H01L2924/13061 ,  H01L2924/13064 ,  H01L2924/146 ,  H01L2924/1461 ,  H01L2924/15747 ,  H01L2924/20102 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106

摘要： Provided is a manufacturing method of a sensor including the following steps. A mold having a cavity is provided. At least one chip is disposed in the cavity. The chip has an active surface and a back surface opposite to each other. The active surface faces toward a bottom surface of the cavity. A polymer material is filled in the cavity to cover the back surface of the chip. A heat treatment is performed, such that the polymer material is solidified to form a polymer substrate. A mold release treatment is performed to isolate the polymer substrate from the cavity. A plurality of conductive lines are formed on a first surface of the polymer substrate. The conductive lines are electrically connected with the chip.

公开(公告)号：US11908816B2

公开(公告)日：2024-02-20

申请号：US17538133

申请日：2021-11-30

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tse-Yao Huang

IPC分类号： H01L23/00

CPC分类号： H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/024 ,  H01L2224/0239 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/0508 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/05193 ,  H01L2224/13026 ,  H01L2924/0105 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0509 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/05994

摘要： The present application discloses a method for fabricating a semiconductor device with graphene layers The method includes providing a substrate; forming a first passivation layer above the substrate; forming a redistribution layer on the first passivation layer; forming a first adjustment layer on the redistribution layer; forming a pad layer on the first adjustment layer; forming a second adjustment layer between the pad layer and the first adjustment layer; forming a second passivation layer on the first passivation layer; wherein the first adjustment layer and the second adjustment layer are formed of graphene.

公开(公告)号：US20230402427A1

公开(公告)日：2023-12-14

申请号：US18447528

申请日：2023-08-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuang-Wei CHENG ,  Chyi-Tsong NI

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/83 ,  H01L25/0657 ,  H01L24/32 ,  H01L25/50 ,  H01L2924/0509 ,  H01L2224/83896 ,  H01L2924/05442 ,  H01L2924/0549 ,  H01L2924/05042 ,  H01L2224/32145

摘要： A first semiconductor device and a second semiconductor device may be directly bonded using heterogeneous bonding layers. A first bonding layer may be formed on the first semiconductor device and the second bonding layer may be formed on the second semiconductor device. The first bonding layer may include a higher concentration of hydroxy-containing silicon relative to the second bonding layer. The second bonding layer may include silicon with a higher concentration of nitrogen relative to the first bonding layer. An anneal may be performed to cause a dehydration reaction that results in decomposition of the hydroxy components of the first bonding layer, which forms silicon oxide bonds between the first bonding layer and the second bonding layer. The nitrogen in the second bonding layer increases the effectiveness of the dehydration reaction and the effectiveness and strength of the bond between the first bonding layer and the second bonding layer.

公开(公告)号：US11935850B2

公开(公告)日：2024-03-19

申请号：US17537931

申请日：2021-11-30

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Kuo-Hui Su

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/05087 ,  H01L2224/05088 ,  H01L2224/05098 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/13026 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01044 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/04541 ,  H01L2924/0455 ,  H01L2924/0469 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0509

摘要： The present application discloses a method for fabricating a semiconductor device with slanted conductive layers. The method for fabricating a semiconductor device includes providing a substrate, forming a first insulating layer above the substrate, forming first slanted recesses along the first insulating layer, and forming first slanted conductive layers in the first slanted recesses and a top conductive layer covering the first slanted conductive layers.

公开(公告)号：US08778773B2

公开(公告)日：2014-07-15

申请号：US12970422

申请日：2010-12-16

申请人： Mariam Sadaka

发明人： Mariam Sadaka

IPC分类号： H01L21/30

CPC分类号： H01L21/76849 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76883 ,  H01L21/76886 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0239 ,  H01L2224/03444 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0381 ,  H01L2224/0384 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05186 ,  H01L2224/05187 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05638 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05687 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/08501 ,  H01L2224/0903 ,  H01L2224/80121 ,  H01L2224/802 ,  H01L2224/80203 ,  H01L2224/80357 ,  H01L2224/80894 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2924/01014 ,  H01L2924/0509 ,  H01L2224/05157 ,  H01L2924/0105 ,  H01L2924/01015 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01025 ,  H01L2924/05042 ,  H01L2924/04642 ,  H01L2924/05442 ,  H01L2224/05552 ,  H01L2924/00

摘要： Embodiments of the present invention include methods of directly bonding together semiconductor structures. In some embodiments, a cap layer may be provided at an interface between directly bonded metal features of the semiconductor structures. In some embodiments, impurities are provided within the directly bonded metal features of the semiconductor structures. Bonded semiconductor structures are formed using such methods.

摘要翻译： 本发明的实施例包括将半导体结构直接结合在一起的方法。 在一些实施例中，盖层可以设置在半导体结构的直接结合的金属特征之间的界面处。 在一些实施例中，在半导体结构的直接结合的金属特征内提供杂质。 使用这种方法形成结合的半导体结构。

公开(公告)号：US09922928B2

公开(公告)日：2018-03-20

申请号：US15217983

申请日：2016-07-23

申请人： Renesas Electronics Corporation

发明人： Takashi Tonegawa

IPC分类号： H01L23/528 ,  H01L21/31 ,  H01L21/44 ,  H01L21/311 ,  H01L23/00 ,  H01L21/3105 ,  H01L23/482 ,  H01L23/522 ,  H01L23/48 ,  H01L23/31 ,  H01L23/532

CPC分类号： H01L23/5283 ,  H01L21/31 ,  H01L21/31056 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/44 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/4827 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/84 ,  H01L24/85 ,  H01L29/1095 ,  H01L29/417 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L2224/02126 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/02206 ,  H01L2224/02215 ,  H01L2224/031 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/03522 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05017 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48799 ,  H01L2224/48844 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/85045 ,  H01L2224/85181 ,  H01L2224/85203 ,  H01L2924/05042 ,  H01L2924/0509 ,  H01L2924/05442 ,  H01L2924/07025 ,  H01L2924/1203 ,  H01L2924/1206 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/00013 ,  H01L2924/059 ,  H01L2924/0103 ,  H01L2924/00

摘要： Properties of a semiconductor device are improved. A semiconductor device is configured so as to have a protective film provided over an interconnection and having an opening, and a plating film provided in the opening. A slit is provided in a side face of the opening, and the plating film is also disposed in the slit. Thus, the slit is provided in the side face of the opening, and the plating film is also grown in the slit. This results in a long penetration path of a plating solution during subsequent formation of the plating film. Hence, a corroded portion is less likely to be formed in the interconnection (pad region). Even if the corroded portion is formed, a portion of the slit is corroded prior to the interconnection (pad region) at a sacrifice, making it possible to suppress expansion of the corroded portion into the interconnection (pad region).

公开(公告)号：US09640509B1

公开(公告)日：2017-05-02

申请号：US15280524

申请日：2016-09-29

申请人： International Business Machines Corporation

发明人： Chih-Chao Yang

IPC分类号： H01L23/00

CPC分类号： H01L24/26 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/32 ,  H01L24/80 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/0341 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/03616 ,  H01L2224/039 ,  H01L2224/04 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/80075 ,  H01L2224/80201 ,  H01L2224/80365 ,  H01L2224/80385 ,  H01L2224/80895 ,  H01L2224/80948 ,  H01L2224/94 ,  H01L2224/08 ,  H01L2224/80 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/04953 ,  H01L2924/01022 ,  H01L2924/0498 ,  H01L2924/01044 ,  H01L2924/01073 ,  H01L2924/0509 ,  H01L2924/0496 ,  H01L2924/01074

摘要： A first semiconductor structure having a first metallic structure that has a convex outermost surface and a second semiconductor structure having a second metallic structure that has a concave outermost surface are first provided. The first and second metallic structures are provided utilizing liner systems that have an opposite galvanic reaction to the metal or metal alloy that constitutes the first and second metallic structures such that during a planarization process the metal liners have a different removal rate than the metal or metal alloy that constitutes the first and second metallic structures. The first semiconductor structure and the second semiconductor structure are then bonded together such that the convex outermost surface of the first metallic structure is in direct contact with the concave outermost surface of the second metallic structure.