公开(公告)号：US20060231025A1

公开(公告)日：2006-10-19

申请号：US11450719

申请日：2006-06-09

申请人： Warren Farnworth ,  Kevin Duesman

发明人： Warren Farnworth ,  Kevin Duesman

IPC分类号： B05C13/00 ,  B05C11/11 ,  B05B5/025

CPC分类号： G03F7/092 ,  B29C64/135 ,  B33Y10/00 ,  B33Y30/00 ,  G03F7/0037 ,  Y10T428/3154

摘要： A programmable material consolidation system includes a platen and an object release element on the platen. The object release element includes a lower surface configured to be secured to the platen and readily removed from the platen. An adhesive coating, which may cover at least a portion of the lower surface, may be formed from a material, such as a radiation-curable polymer, that is tacky when in an uncured state and not as tacky when in a substantially cured state. A nonstick coating on the platen may facilitate ready removal of the object release element therefrom. An upper surface of the object release element may include a material to which an object will adhere, but which may be readily removed from the object once fabrication thereof is complete.

摘要翻译： 可编程材料固结系统包括压板和压板上的物体释放元件。 物体释放元件包括被配置为固定到压板并容易地从压板移除的下表面。 可以覆盖下表面的至少一部分的粘合剂涂层可以由诸如可辐射固化聚合物的材料形成，其在处于未固化状态时是发粘的，并且在基本固化的状态下不发粘。 压板上的不粘涂层可以有助于从其中准备去除物体释放元件。 物体释放元件的上表面可以包括物体将被粘附的材料，但是一旦制造完成，其可以容易地从物体移除。

公开(公告)号：US20060226578A1

公开(公告)日：2006-10-12

申请号：US11450742

申请日：2006-06-09

申请人： Warren Farnworth ,  Kevin Duesman

发明人： Warren Farnworth ,  Kevin Duesman

IPC分类号： B29C35/08 ,  B29C41/02 ,  B29C33/68

CPC分类号： G03F7/092 ,  B29C64/135 ,  B33Y10/00 ,  B33Y30/00 ,  G03F7/0037 ,  Y10T428/3154

摘要： A programmed material consolidation method includes use of an object release element for facilitate removal of an object from a platen of programmed material consolation equipment while leaving substantially no residue on the platen or a fabricated object, and without requiring substantial post-release modification of the fabricated object. The object release element may be adhesively secured to a non-stick surface of the platen, with a material that adheres to the platen before being cured and that may be removed from the platen upon curing, or by application of a negative pressure through the platen to the object release element. The object release element may be formed from a material or include coating of a material, such as polyethylene, polyethyleneteraphthalate, or polyethylene ethyl ketone, that adheres to a fabricated object, but may be readily released from the fabricated object (e.g., by peeling).

摘要翻译： 编程材料固结方法包括使用物体释放元件，用于便于从编程材料安慰设备的台板移除物体，同时在压板或制造的物体上基本上没有残留物，并且不需要对所制造的材料进行实质的后释放改性 目的。 物体释放元件可以粘合地固定到压板的不粘表面，其具有在固化之前粘附到压板的材料，并且可以在固化时从压板移除，或者通过施加负压通过压板 到对象释放元件。 物体释放元件可以由材料形成，或者包括粘附到制造的物体上但可以容易地从制造的物体（例如通过剥离）释放的材料（例如聚乙烯，聚对苯二甲酸乙二醇酯或聚乙烯乙基酮）的涂层， 。

公开(公告)号：US20060186317A1

公开(公告)日：2006-08-24

申请号：US11404831

申请日：2006-04-17

申请人： Warren Farnworth ,  Sidney Rigg ,  David Hembree ,  William Hiatt

发明人： Warren Farnworth ,  Sidney Rigg ,  David Hembree ,  William Hiatt

IPC分类号： H01L27/00

CPC分类号： H01L31/0203 ,  B33Y80/00 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14689 ,  H01L27/148 ,  H01L2224/48227 ,  H01L2224/48091 ,  H01L2924/00014

摘要： Microelectronic imagers with prefabricated housings and methods of packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imager can include a microelectronic die, an image sensor, and an integrated circuit operatively coupled to the integrated circuit. The microelectronic imager also includes an optic unit having an optic member. The microelectronic imager further includes a prefabricated housing having a first mounting site and a second mounting site. The die is seated within the housing at the first mounting site and the optics unit is seated within the housing at the second mounting site in a fixed, preset position in which the optic member is situated at a desired location relative to the image sensor.

摘要翻译： 具有预制外壳的微电子成像器和封装微电子成像器的方法在此公开。 在一个实施例中，微电子成像器可以包括微电子管芯，图像传感器和可操作地耦合到集成电路的集成电路。 微电子成像器还包括具有光学构件的光学单元。 微电子成像器还包括具有第一安装位置和第二安装位置的预制外壳。 模具位于第一安装位置的壳体内，并且光学单元在第二安装位置处位于壳体内的固定的预设位置中，光学构件位于相对于图像传感器的期望位置处。

公开(公告)号：US20060183349A1

公开(公告)日：2006-08-17

申请号：US11390321

申请日：2006-03-27

申请人： Warren Farnworth ,  Alan Wood ,  Trung Doan

发明人： Warren Farnworth ,  Alan Wood ,  Trung Doan

IPC分类号： H01L21/31 ,  H01L23/28 ,  H01L23/34

CPC分类号： H01L23/48 ,  B33Y70/00 ,  B33Y80/00 ,  H01L21/304 ,  H01L21/3043 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76802 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/24 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/3672 ,  H01L23/481 ,  H01L23/49531 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/27 ,  H01L24/94 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/274 ,  H01L2224/73104 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/27

摘要： A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit side polymer layer, and terminal contacts on the contact bumps in a dense area array. A method for fabricating the component includes the steps of providing a substrate containing multiple dice, forming trenches on the substrate proximate to peripheral edges of the dice, and depositing a polymer material into the trenches. In addition, the method includes the steps of planarizing the back side of the substrate to contact the polymer filled trenches, and cutting through the polymer trenches to singulate the components from the substrate. Prior to the singulating step the components can be tested and burned-in while they remain on the substrate.

摘要翻译： 半导体部件包括在六个表面上具有保护性聚合物层的变薄的半导体管芯。 该组件还包括嵌入在电路侧聚合物层中的裸片上的接触凸块，并且密集区域阵列中接触凸块上的端子接触。 一种用于制造该部件的方法包括以下步骤：提供包含多个骰子的基底，在基底上邻近骰子的周边边缘形成沟槽，以及将聚合物材料沉积到沟槽中。 此外，该方法包括以下步骤：平坦化衬底的背面以接触聚合物填充的沟槽，并切割穿过聚合物沟槽以从衬底中分离组分。 在分离步骤之前，组分可以在它们保留在基材上时被测试和燃烧。

公开(公告)号：US20060181298A1

公开(公告)日：2006-08-17

申请号：US11057500

申请日：2005-02-14

申请人： Warren Farnworth ,  Mark Tuttle

发明人： Warren Farnworth ,  Mark Tuttle

IPC分类号： G01R31/26

CPC分类号： G01R31/2886

摘要： A method for testing a semiconductor component includes the steps of bonding an interconnect to the component to form bonded electrical connections, applying test signals through the bonded electrical connections, and then separating the interconnect from the component. The bonding step can be performed using metallurgical bonding, and the separating step can be performed using solder-wettable and solder non-wettable metal layers on the interconnect or the component. During the separating step the solder-wettable layers are dissolved, reducing adhesion of the bonded electrical connections, and permitting separation of the component and interconnect. The interconnect includes interconnect contacts configured for bonding to, and then separation from component contacts on the components. A system includes the interconnect, an alignment system for aligning the substrate to the interconnect, a bonding system for bonding the component to the interconnect, and a heating system for heating the component and the interconnect for separation.

摘要翻译： 用于测试半导体部件的方法包括以下步骤：将互连件连接到部件以形成结合的电连接，通过结合的电连接施加测试信号，然后将该互连件与部件分离。 接合步骤可以使用冶金结合进行，并且分离步骤可以使用在互连或部件上的可焊接润湿和焊接不可润湿的金属层进行。 在分离步骤期间，可焊接润湿层被溶解，减少了粘合的电连接的粘合性，并允许部件和互连的分离。 互连包括被配置用于结合到组件上并且然后与组件上的组件触点分离的互连触点。 系统包括互连，用于将衬底对准互连的对准系统，用于将组件粘合到互连的接合系统，以及用于加热组件和用于分离的互连的加热系统。

公开(公告)号：US20060163318A1

公开(公告)日：2006-07-27

申请号：US11387162

申请日：2006-03-23

申请人： Warren Farnworth

发明人： Warren Farnworth

IPC分类号： B23K1/00 ,  B23K31/02 ,  B23K20/08

CPC分类号： H01L21/6715 ,  B22F2009/0836 ,  B23K3/0623 ,  B23K20/004 ,  B23K2101/40 ,  B41J2/085 ,  B41J2/09 ,  G01N33/6842 ,  H01L21/67144 ,  H05K3/3457 ,  H05K2203/013 ,  H05K2203/105

摘要： A solder jet apparatus and method is disclosed. The solder jet apparatus is a continuous mode solder jet that includes a blanking system and raster scan system. The use of the raster scan and blanking systems allows for a continuous stream of solder to be placed anywhere on the surface in any desired X-Y plane. This allows for greater accuracy as well as greater product throughput. Additionally, with the raster scan system, repairs to existing soldered surfaces can be quickly and easily performed using a map of the defects for directing the solder to the defects.

摘要翻译： 公开了一种焊料喷射装置和方法。 焊料喷射装置是包括消隐系统和光栅扫描系统的连续模式焊料喷射。 光栅扫描和消隐系统的使用允许将连续的焊料流放置在任何所需的X-Y平面上的任何地方。 这允许更高的精度以及更大的产品吞吐量。 另外，使用光栅扫描系统，可以使用用于将焊料引导到缺陷的缺陷图快速轻松地进行现有焊接表面的修复。

公开(公告)号：US20060115932A1

公开(公告)日：2006-06-01

申请号：US11332929

申请日：2006-01-17

申请人： Warren Farnworth ,  Alan Wood ,  David Hembree

发明人： Warren Farnworth ,  Alan Wood ,  David Hembree

IPC分类号： H01L21/50 ,  H01L21/48 ,  H01L21/44

CPC分类号： H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2224/82039 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1005 ,  H01L2225/1058 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/0029 ,  H05K3/0032 ,  H05K2201/09472 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09845 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00

摘要： A method for fabricating semiconductor components and interconnects includes the steps of providing a substrate, such as a semiconductor die, forming external contacts on opposing sides of the substrate by laser drilling vias through the substrate, and forming conductive members in the vias. The conductive members include enlarged terminal portions that are covered with a non-oxidizing metal. The method can be used to fabricate stackable semiconductor packages having integrated circuits in electrical communication with the external contacts. The method can also be used to fabricate interconnects for electrically engaging packages, dice and wafers for testing or for constructing electronic assemblies.

摘要翻译： 一种用于制造半导体部件和互连的方法包括以下步骤：提供诸如半导体管芯的衬底，通过穿过衬底的激光钻孔通孔在衬底的相对侧上形成外部触点，以及在通孔中形成导电构件。 导电构件包括被非氧化金属覆盖的扩大端子部分。 该方法可用于制造具有与外部触点电连通的集成电路的可堆叠半导体封装。 该方法还可用于制造用于电接合封装，裸片和晶片用于测试或构建电子组件的互连。

公开(公告)号：US20060043599A1

公开(公告)日：2006-03-02

申请号：US10932296

申请日：2004-09-02

申请人： Salman Akram ,  Charles Watkins ,  Mark Hiatt ,  David Hembree ,  James Wark ,  Warren Farnworth ,  Mark Tuttle ,  Sidney Rigg ,  Steven Oliver ,  Kyle Kirby ,  Alan Wood ,  Lu Velicky

发明人： Salman Akram ,  Charles Watkins ,  Mark Hiatt ,  David Hembree ,  James Wark ,  Warren Farnworth ,  Mark Tuttle ,  Sidney Rigg ,  Steven Oliver ,  Kyle Kirby ,  Alan Wood ,  Lu Velicky

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L21/76877 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/45 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

公开(公告)号：US20060043598A1

公开(公告)日：2006-03-02

申请号：US10931959

申请日：2004-08-31

申请人： Kyle Kirby ,  Warren Farnworth

发明人： Kyle Kirby ,  Warren Farnworth

IPC分类号： H01L23/48

CPC分类号： B82Y10/00 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/1094 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2224/05599 ,  H01L2224/05099

摘要： Methods of forming at least one multiconductor via are disclosed. Specifically, a substrate may be provided and at least one through-hole may be formed therethrough. At least one seed layer may be formed, patterned, and a metal may be deposited thereon to form a plurality of conductive elements. Alternatively, the at least one through-hole may be substantially filled with a dielectric material and a plurality of smaller through-holes may be formed therein and then filled with conductive material to form a plurality of conductive elements. Alternatively, at least one cavity may be formed into a substrate and a plurality of conductive nanotubes or other protruding structures may be formed therein. The substrate may be thinned to form at least one through-hole and a plurality of laterally separated conductive elements extending therethrough. Semiconductor dice, substrates, as well as multichip modules having dice including multiconductor vias, systems including same, and methods of manufacture are also disclosed.

摘要翻译： 公开了形成至少一个多导体通孔的方法。 具体地，可以设置基板，并且可以形成至少一个通孔。 可以形成至少一个种子层，图案化，并且可以在其上沉积金属以形成多个导电元件。 或者，至少一个通孔可以基本上填充有介电材料，并且可以在其中形成多个较小的通孔，然后填充导电材料以形成多个导电元件。 或者，可以将至少一个空腔形成为基板，并且可以在其中形成多个导电纳米管或其它突出结构。 基板可以被薄化以形成至少一个通孔和多个横向分离的导电元件延伸穿过其中。 还公开了半导体晶片，衬底以及具有多导体通孔的芯片的多芯片模块，包括其的系统和制造方法。

公开(公告)号：US20060033190A1

公开(公告)日：2006-02-16

申请号：US11257428

申请日：2005-10-24

申请人： Larry Kinsman ,  Walter Moden ,  Warren Farnworth

发明人： Larry Kinsman ,  Walter Moden ,  Warren Farnworth

IPC分类号： H01L23/02

CPC分类号： H05K3/301 ,  H01L25/105 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K2201/10454 ,  H05K2201/10696 ,  Y10S83/942 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49147 ,  Y10T29/49156 ,  Y10T29/49169 ,  Y10T29/53174 ,  Y10T29/53178 ,  H01L2924/00

摘要： A semiconductor device package includes a die, a package encapsulating at least a portion of the die, and a plurality of leads. Each lead of the plurality includes an external portion. The external portion of each lead is substantially planar and extends outward from a bottom edge of the package. The external portion of each lead may be oriented in a plane that is substantially parallel to a plane within which the die is located. A semiconductor device including these features may be part of an assembly that also includes an alignment device for orienting the semiconductor device package in nonparallel relation to a substrate.

摘要翻译： 半导体器件封装包括管芯，封装至少一部分裸片的封装以及多个引线。 多个的每个引线包括外部部分。 每个引线的外部部分基本上是平面的并且从封装的底部边缘向外延伸。 每个引线的外部部分可以在基本上平行于管芯所在的平面的平面内取向。 包括这些特征的半导体器件可以是组件的一部分，该组件还包括用于将半导体器件封装以非平行关系定向到衬底的对准装置。