公开(公告)号：US20240153896A1

公开(公告)日：2024-05-09

申请号：US18411314

申请日：2024-01-12

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Hui-Min Huang ,  Chih-Wei Lin ,  Tsai-Tsung Tsai ,  Ming-Da Cheng ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L24/05 ,  H01L21/481 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/49866 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L21/568 ,  H01L23/49827 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/83191 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/18162

Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.

公开(公告)号：US20240125713A1

公开(公告)日：2024-04-18

申请号：US18152409

申请日：2023-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao Chun Yang ,  Ming-Da Cheng ,  Pei-Wei Lee ,  Mirng-Ji Lii

IPC: G01N21/95 ,  G01N21/59

CPC classification number: G01N21/9505 ,  G01N21/59 ,  G01N2201/06113 ,  G01N2201/0636

Abstract: A method includes directing light at a first side of a semiconductor structure; detecting a first light intensity at a second side of the semiconductor structure, wherein the first light intensity corresponds to the light that penetrated the semiconductor structure from the first side to the second side; and comparing the first light intensity to a second light intensity, wherein the second light intensity corresponds to an expected intensity of light.

公开(公告)号：US11961762B2

公开(公告)日：2024-04-16

申请号：US17809960

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Tzy-Kuang Lee ,  Song-Bor Lee ,  Wen-Hsiung Lu ,  Po-Hao Tsai ,  Wen-Che Chang

IPC: H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76885 ,  H01L21/76802 ,  H01L21/76852 ,  H01L21/76871 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022

Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.

公开(公告)号：US20240096827A1

公开(公告)日：2024-03-21

申请号：US18526057

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Shien Chen ,  Ting-Li Yang ,  Po-Hao Tsai ,  Chien-Chen Li ,  Ming-Da Cheng

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L24/05 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/16 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0236 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/16225

Abstract: In an embodiment, a device includes: a passivation layer on a semiconductor substrate; a first redistribution line on and extending along the passivation layer; a second redistribution line on and extending along the passivation layer; a first dielectric layer on the first redistribution line, the second redistribution line, and the passivation layer; and an under bump metallization having a bump portion and a first via portion, the bump portion disposed on and extending along the first dielectric layer, the bump portion overlapping the first redistribution line and the second redistribution line, the first via portion extending through the first dielectric layer to be physically and electrically coupled to the first redistribution line.

公开(公告)号：US20230411318A1

公开(公告)日：2023-12-21

申请号：US18231032

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Ming-Da Cheng ,  Yung-Han Chuang ,  Hsueh-Sheng Wang

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/14 ,  H01L24/11 ,  H01L2924/3841 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/06051 ,  H01L2224/0231 ,  H01L2224/03462 ,  H01L2224/11849 ,  H01L2224/0603 ,  H01L2224/02331 ,  H01L2224/05017 ,  H01L2224/1403 ,  H01L2224/14051

Abstract: Methods for forming under-bump metallurgy (UBM) structures having different surface profiles and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a first under-bump metallurgy (UBM) structure over and electrically coupled to the first redistribution line, the first UBM structure extending through the first passivation layer, a top surface of the first UBM structure being concave; and a second UBM structure over and electrically coupled to the second redistribution line, the second UBM structure extending through the first passivation layer, a top surface of the second UBM structure being flat or convex.

公开(公告)号：US11842935B2

公开(公告)日：2023-12-12

申请号：US17318703

申请日：2021-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Shien Chen ,  Kuo-Ching Hsu ,  Wei-Hung Lin ,  Hui-Min Huang ,  Ming-Da Cheng ,  Mirng-Ji Lii

IPC: H01L23/31 ,  H01L23/538 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/3114 ,  H01L21/56 ,  H01L23/5384 ,  H01L24/81

Abstract: A method includes forming a reconstructed package substrate, which includes placing a plurality of substrate blocks over a carrier, encapsulating the plurality of substrate blocks in an encapsulant, planarizing the encapsulant and the plurality of substrate blocks to reveal redistribution lines in the plurality of substrate blocks, and forming a redistribution structure overlapping both of the plurality of substrate blocks and encapsulant. A package component is bonded over the reconstructed package substrate.

公开(公告)号：US20230378052A1

公开(公告)日：2023-11-23

申请号：US18365009

申请日：2023-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ming Huang ,  Ming-Da Cheng ,  Songbor Lee ,  Jung-You Chen ,  Ching-Hua Kuan ,  Tzy-Kuang Lee

IPC: H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5223 ,  H01L24/03 ,  H01L23/5226 ,  H01L28/60 ,  H01L2224/02313 ,  H01L2224/02311

Abstract: A method includes depositing a first passivation layer over a conductive feature, wherein the first passivation layer has a first dielectric constant, forming a capacitor over the first passivation layer, and depositing a second passivation layer over the capacitor, wherein the second passivation layer has a second dielectric constant greater than the first dielectric constant. The method further includes forming a redistribution line over and electrically connecting to the capacitor, depositing a third passivation layer over the redistribution line, and forming an Under-Bump-Metallurgy (UBM) penetrating through the third passivation layer to electrically connect to the redistribution line.

公开(公告)号：US20230369049A1

公开(公告)日：2023-11-16

申请号：US18350583

申请日：2023-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Jung Hsueh ,  Chen-En Yen ,  Chin Wei Kang ,  Kai Jun Zhan ,  Wei-Hung Lin ,  Cheng Jen Lin ,  Ming-Da Cheng ,  Ching-Hui Chen ,  Mirng-Ji Lii

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/31144 ,  H01L21/31058 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/0273

Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.

公开(公告)号：US20230290809A1

公开(公告)日：2023-09-14

申请号：US17828844

申请日：2022-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mei-Chi Lee ,  Chi-Cheng Chen ,  Wei-Li Huang ,  Kai Tzeng ,  Chun Yi Wu ,  Ming-Da Cheng

IPC: H01L49/02

CPC classification number: H01L28/10

Abstract: A method of forming a semiconductor device includes: forming a passivation layer over a conductive pad that is disposed over a substrate; and forming an inductive component over the passivation layer, including: forming a first insulation layer and a first magnetic layer successively over the passivation layer; forming a first polymer layer over the first magnetic layer; forming a first conductive feature over the first polymer layer; forming a second polymer layer over the first polymer layer and the first conductive feature; patterning the second polymer layer, where after the patterning, a first sidewall of the second polymer layer includes multiple segments, where an extension of a first segment of the multiple segments intersects the second polymer layer; and after patterning the second polymer layer, forming a second insulation layer and a second magnetic layer successively over the second polymer layer.

公开(公告)号：US11545465B2

公开(公告)日：2023-01-03

申请号：US17113676

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Hui-Min Huang ,  Hsuan-Ting Kuo ,  Ming-Da Cheng

IPC: H01L23/02 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.