公开(公告)号：US20180040727A1

公开(公告)日：2018-02-08

申请号：US15789620

申请日：2017-10-20

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Brent A. Anderson ,  Fee Li Lie ,  Junli Wang

IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L21/02 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8234

CPC分类号： H01L29/785 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/31056 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827

摘要： A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned shallow trench isolation region, including forming a pinch-off layer on one or more vertical fin segments, wherein the pinch-off layer has a thickness on the sidewalls of the one or more vertical fin segments, forming a trench mask layer on predetermined portions of the pinch-off layer, removing portions of the pinch-off layer not covered by the trench mask layer, where the removed portions of the pinch-off layer exposes underlying portions of the substrate, and removing at least a portion of the substrate to form one or more isolation region trenches, where the distance of the sidewall of one of the one or more isolation region trenches to an adjacent vertical fin segment is determined by the thickness of the pinch-off layer.

公开(公告)号：US20180033633A1

公开(公告)日：2018-02-01

申请号：US15220365

申请日：2016-07-26

申请人： UNITED MICROELECTRONICS CORP.

发明人： Fu-Shou Tsai ,  Yu-Ting Li ,  Li-Chieh Hsu ,  Yi-Liang Liu ,  Kun-Ju Li ,  Po-Cheng Huang ,  Chien-Nan Lin

IPC分类号： H01L21/308 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/027

CPC分类号： H01L21/3081 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0273 ,  H01L21/302 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31056 ,  H01L21/31058 ,  H01L21/3212

摘要： A method for planarizing a silicon layer includes providing a silicon layer having at least one recess therein. Next, a photoresist layer is formed to cover the silicon layer and fill up the recess. Then, the photoresist layer is hardened. After that, part of the photoresist layer is removed by taking a top surface of the silicon layer as a stop layer. Finally the photoresist layer and the silicon layer are etched back simultaneously to remove the photoresist layer entirely.

公开(公告)号：US09853078B2

公开(公告)日：2017-12-26

申请号：US15280657

申请日：2016-09-29

申请人： SK hynix Inc.

发明人： Yun-Hui Yang ,  Sung-Bo Hwang ,  Young-Hun Choi

IPC分类号： H01L21/3105 ,  H01L27/146

CPC分类号： H01L27/14632 ,  H01L21/31053 ,  H01L21/31056 ,  H01L27/14618 ,  H01L27/1462 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14636

摘要： A wafer level curved image sensor may include a substrate having a central region, a peripheral region, and an edge region, the peripheral region being formed between the central region and the edge region, supporting patterns formed over the substrate, first fixed patterns formed between the supporting patterns, and an image sensing chip formed over the supporting patterns. The supporting patterns and the first fixed patterns, in combination, form a planar lower surface and a concavely-curved upper surface. The image sensing chip has a curved lower surface and a curved upper surface.

公开(公告)号：US20170338160A1

公开(公告)日：2017-11-23

申请号：US15667978

申请日：2017-08-03

申请人： Lam Research Corporation

发明人： Yassine Kabouzi ,  Luc Albarede ,  Andrew D. Bailey, III ,  Jorge Luque ,  Seonkyung Lee ,  Thorsten Lill

IPC分类号： H01L21/66 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3105

CPC分类号： H01L22/26 ,  H01J37/32981 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/32137 ,  H01L28/00

摘要： A method for dry processing a substrate in a processing chamber is provided. The substrate is placed in the processing chamber. The substrate is dry processed, wherein the dry processing creates at least one gas byproduct. A concentration of the at least one gas byproduct is measured. The concentration of the at least one gas byproduct is used to determine processing rate of the substrate.

公开(公告)号：US20170316935A1

公开(公告)日：2017-11-02

申请号：US15494245

申请日：2017-04-21

申请人： Lam Research Corporation

发明人： Samantha Tan ,  Jengyi Yu ,  Richard Wise ,  Nader Shamma ,  Yang Pan

IPC分类号： H01L21/027 ,  H01L21/3105 ,  H01J37/32 ,  G03F7/42 ,  H01L21/311

CPC分类号： H01L21/0273 ,  G03F7/427 ,  H01J37/32183 ,  H01J37/3244 ,  H01J37/32899 ,  H01J2237/334 ,  H01L21/02115 ,  H01L21/3065 ,  H01L21/31056 ,  H01L21/31058 ,  H01L21/31138

摘要： Methods of and apparatuses for processing substrates having carbon-containing material using atomic layer deposition and selective deposition are provided. Methods involve exposing a carbon-containing material on a substrate to an oxidant and igniting a first plasma at a first bias power to modify a surface of the substrate and exposing the modified surface to an inert plasma at a second bias power to remove the modified surface. Methods also involve selectively depositing a second carbon-containing material onto the substrate. ALE and selective deposition may be performed without breaking vacuum.

公开(公告)号：US09735069B2

公开(公告)日：2017-08-15

申请号：US14862983

申请日：2015-09-23

申请人： Lam Research Corporation

发明人： Yassine Kabouzi ,  Luc Albarede ,  Andrew D. Bailey, III ,  Jorge Luque ,  Seonkyung Lee ,  Thorsten Lill

IPC分类号： H01L21/302 ,  H01L21/461 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/66 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/308 ,  H01L21/3105

CPC分类号： H01L22/26 ,  H01J37/32981 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/32137 ,  H01L28/00

摘要： A method for dry processing a substrate in a processing chamber is provided. The substrate is placed in the processing chamber. The substrate is dry processed, wherein the dry processing creates at least one gas byproduct. A concentration of the at least one gas byproduct is measured. The concentration of the at least one gas byproduct is used to determine processing rate of the substrate.

公开(公告)号：US09633855B2

公开(公告)日：2017-04-25

申请号：US14722022

申请日：2015-05-26

申请人： Institute of Microelectronics, Chinese Academy of Sciences

发明人： Huilong Zhu

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/768 ,  C23C14/34 ,  H01L21/8234

CPC分类号： H01L21/28017 ,  C23C14/34 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/32131 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/823456 ,  H01L29/66545

摘要： Planarization processing methods are disclosed. In one aspect, the method includes patterning a material layer and planarizing the patterned material layer by using sputtering. Due to the patterning of the material layer, the loading requirements of nonuniformity on a substrate for sputtering the material layer are reduced, compared with that before the patterning.

公开(公告)号：US09627322B2

公开(公告)日：2017-04-18

申请号：US14828639

申请日：2015-08-18

申请人： International Business Machines Corporation

发明人： Injo Ok ,  Balasubramanian S. Pranatharthiharan ,  Charan V. Surisetty

IPC分类号： H01L23/535 ,  H01L21/768 ,  H01L21/3105 ,  H01L23/485 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088

CPC分类号： H01L23/535 ,  H01L21/31056 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53266 ,  H01L27/0207 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device including at least one self-aligned contact has at least one gate electrode on a bulk substrate layer of the semiconductor device. A gate cap encapsulates the at least one gate electrode. The semiconductor device further includes at least one contact separated from the at least one gate electrode via a portion of the gate cap. The at least one contact includes a metal portion that directly contacts the gate cap.

公开(公告)号：US20170084747A1

公开(公告)日：2017-03-23

申请号：US15368812

申请日：2016-12-05

申请人： Semiconductor Manufacturing International (Shanghai) Corporation

发明人： HAIYANG ZHANG ,  CHENGLONG ZHANG

IPC分类号： H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/7856 ,  H01L21/265 ,  H01L21/3086 ,  H01L21/31 ,  H01L21/31056 ,  H01L21/32135 ,  H01L29/495 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66795

摘要： A method for fabricating a FinFET structure comprises providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate; forming a dummy gate structure having a dummy gate, a first sidewall spacer and a second sidewall spacer; removing the dummy gate to form a first trench; forming first sub-fins in the semiconductor substrate under the hard mask layer in the first trench; forming a first metal gate structure in the first trench; removing the first sidewall spacer to form a second trench; forming second sub-fins in the semiconductor substrate under the hard mask layer in the second trench; forming a second metal gate structure in the second trench; removing the second sidewall spacer to form a third trench; forming third sub-fins in the semiconductor substrate under the hard mask layer in the third trench; and forming a third metal gate structure in the third trench.

公开(公告)号：US20170077036A1

公开(公告)日：2017-03-16

申请号：US15361757

申请日：2016-11-28

申请人： International Business Machines Corporation

发明人： Josephine B. Chang ,  Szu-Lin Cheng ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC分类号： H01L23/532 ,  H01L21/3105 ,  H01L23/528 ,  H01L21/02

CPC分类号： H01L23/53228 ,  H01L21/02134 ,  H01L21/02282 ,  H01L21/02351 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/324 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one aspect, a method of forming a wiring layer on a wafer is provided which includes: depositing a HSQ layer onto the wafer; cross-linking a first portion(s) of the HSQ layer using e-beam lithography; depositing a hardmask material onto the HSQ layer; patterning the hardmask using optical lithography, wherein the patterned hardmask covers a second portion(s) of the HSQ layer; patterning the HSQ layer using the patterned hardmask in a manner such that i) the first portion(s) of the HSQ layer remain and ii) the second portion(s) of the HSQ layer covered by the patterned hardmask remain, wherein by way of the patterning step trenches are formed in the HSQ layer; and filling the trenches with a conductive material to form the wiring layer on the wafer.

摘要翻译： 一方面，提供了一种在晶片上形成布线层的方法，包括：将HSQ层沉积到晶片上; 使用电子束光刻术交联HSQ层的第一部分; 将硬掩模材料沉积到HSQ层上; 使用光学平版印刷图案化硬掩模，其中图案化的硬掩模覆盖HSQ层的第二部分; 使用图案化的硬掩模以使得i）HSQ层的第一部分保留并且ii）被图案化硬掩模覆盖的HSQ层的第二部分保留的方式图案化HSQ层，其中通过 图案化步骤沟槽形成在HSQ层中; 并用导电材料填充沟槽以在晶片上形成布线层。