公开(公告)号：US08174353B2

公开(公告)日：2012-05-08

申请号：US12235437

申请日：2008-09-22

申请人： Tae-Hoon Jeong ,  Kyo-Sung Ji ,  Jung-Soo Kim ,  Jung-Hwan Kim ,  Sung-Wook Choi

发明人： Tae-Hoon Jeong ,  Kyo-Sung Ji ,  Jung-Soo Kim ,  Jung-Hwan Kim ,  Sung-Wook Choi

IPC分类号： H01C7/10

CPC分类号： H01C1/022 ,  H01C1/144 ,  H01C7/126

摘要： A varistor comprises a main body having first and second external terminals formed on the outer surface thereof, a first withdrawn terminal plate joined to the first external terminal, and a second withdrawn terminal plate joined to the second external terminal, wherein the melting point of a second bonding material for allowing the second withdrawn terminal plate and the second external terminal to be joined to each other is lower than that of a first bonding material for allowing the first withdrawn terminal plate and the first external terminal to be joined to each other.

摘要翻译： 变阻器包括：主体，其外表面上形成有第一和第二外部端子，与第一外部端子接合的第一引出端子板和与第二外部端子连接的第二抽出端子板，其中熔点 用于使第二取出端子板和第二外部端子彼此接合的第二接合材料低于用于使第一取出端子板和第一外部端子彼此接合的第一接合材料的接合材料。

公开(公告)号：US20120083097A1

公开(公告)日：2012-04-05

申请号：US13187760

申请日：2011-07-21

申请人： Ju-il Choi ,  Kyu-Ha Lee ,  Jae-Hyun Phee ,  Jung-Hwan Kim ,  Tae Hong Min

发明人： Ju-il Choi ,  Kyu-Ha Lee ,  Jae-Hyun Phee ,  Jung-Hwan Kim ,  Tae Hong Min

IPC分类号： H01L21/78

CPC分类号： H01L21/78 ,  H01L21/486 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2224/02372 ,  H01L2224/1146 ,  H01L2224/116 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81903 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2224/81 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599

摘要： Provided is a method of forming a semiconductor package including providing a substrate having a first side and an opposite second side and providing a wafer having a plurality of semiconductor chips, each of the semiconductor chips having a conductive pad, wherein at least one of the substrate and the wafer includes a seed pattern. The first side of the substrate is bonded to the wafer with the conductive pad positioned adjacent to the first side of the substrate and the seed pattern positioned between the conductive pad and the first side of the substrate. A through hole is then formed penetrating the substrate from the second side of the substrate to expose the seed pattern. A through electrode is formed in the through hole using the seed pattern as a seed. Corresponding devices are also provided.

摘要翻译： 提供一种形成半导体封装的方法，包括提供具有第一侧和相对的第二侧的衬底，并提供具有多个半导体芯片的晶片，每个半导体芯片具有导电焊盘，其中至少一个衬底 并且晶片包括种子图案。 衬底的第一面被接合到晶片，其中导电焊盘定位成与衬底的第一侧相邻，并且种子图案位于导电焊盘和衬底的第一侧之间。 然后从衬底的第二侧穿透衬底以形成通孔以暴露种子图案。 使用种子图案作为种子在通孔中形成贯通电极。 还提供了相应的设备。

公开(公告)号：US20120018871A1

公开(公告)日：2012-01-26

申请号：US13183645

申请日：2011-07-15

申请人： Chung-sun LEE ,  Jung-Hwan Kim ,  Yun-Hyeok Im ,  Ji-Hwan Hwang ,  Hyon-chol Kim ,  Kwang-chul Choi ,  Eun-Kyong Choi ,  Tae-hong Min

发明人： Chung-sun LEE ,  Jung-Hwan Kim ,  Yun-Hyeok Im ,  Ji-Hwan Hwang ,  Hyon-chol Kim ,  Kwang-chul Choi ,  Eun-Kyong Choi ,  Tae-hong Min

IPC分类号： H01L23/58

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A stack package usable in a three-dimensional (3D) system-in-package (SIP) includes a first semiconductor chip, a second semiconductor chip, and a supporter. The first semiconductor chip includes a through silicon via (TSV), and the second semiconductor chip is stacked on the first semiconductor chip and is electrically connected to the first semiconductor chip through the TSV of the first semiconductor chip. The supporter is attached onto the first semiconductor chip so as to be spaced apart from an edge of the second semiconductor chip.

摘要翻译： 可用于三维（3D）系统级封装（SIP））的堆叠封装包括第一半导体芯片，第二半导体芯片和支持器。 第一半导体芯片包括贯通硅通孔（TSV），第二半导体芯片堆叠在第一半导体芯片上，并通过第一半导体芯片的TSV与第一半导体芯片电连接。 支撑件附接到第一半导体芯片上，以便与第二半导体芯片的边缘间隔开。

公开(公告)号：US20110233755A1

公开(公告)日：2011-09-29

申请号：US13072012

申请日：2011-03-25

申请人： Dong-Han Kim ,  Sung-Woo Park ,  Jin-Woo Park ,  So-Young Lim ,  Jung-Hwan Kim ,  Kwang-Jin Bae ,  Pa-Lan Lee

发明人： Dong-Han Kim ,  Sung-Woo Park ,  Jin-Woo Park ,  So-Young Lim ,  Jung-Hwan Kim ,  Kwang-Jin Bae ,  Pa-Lan Lee

IPC分类号： H01L23/48

CPC分类号： H01L25/105 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/05171 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73277 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10157 ,  H01L2924/10158 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor housing package may be provided. The semiconductor housing package may include a mold layer, a housing chip, a redistribution structure, and a housing node. The mold layer may surround and partially expose the housing chip. The redistribution structure may be electrically connected to the housing chip and may be disposed on the mold layer. The housing node may be in contact with the redistribution structures. The semiconductor housing package may be disposed on a semiconductor base package and may constitute a semiconductor package structure along with the semiconductor base package. The semiconductor package structure may be disposed on a processor-based system.

摘要翻译： 可以提供半导体外壳封装。 半导体外壳封装可以包括模具层，壳体芯片，再分布结构和壳体节点。 模具层可围绕并部分地暴露外壳芯片。 再分布结构可以电连接到壳体芯片并且可以设置在模具层上。 壳体节点可以与再分布结构接触。 半导体外壳封装可以设置在半导体基底封装上，并且可以与半导体基底封装构成半导体封装结构。 半导体封装结构可以设置在基于处理器的系统上。

公开(公告)号：US20110097836A1

公开(公告)日：2011-04-28

申请号：US12982252

申请日：2010-12-30

申请人： Eun-Hong KIM ,  Bong-Mook Yim ,  Jung-Hwan Kim

发明人： Eun-Hong KIM ,  Bong-Mook Yim ,  Jung-Hwan Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/1288 ,  G02F1/136259 ,  G02F2001/136263 ,  G02F2001/136272 ,  H01L27/1214

摘要： An array substrate includes a substrate, a gate line on the substrate, a data line crossing the gate line to define a pixel region, a thin film transistor connected to the gate and data lines, a pixel electrode in the pixel region, and a common electrode including first, second, third, fourth and fifth portions, wherein the first and second portions are disposed at both sides of the data line, each of the third and fourth portions is connected to the first and second portions, and the fifth portion is connected to the second portion and is extended into a next pixel region adjacent to the pixel region.

摘要翻译： 阵列基板包括基板，基板上的栅极线，与栅极线交叉以限定像素区域的数据线，连接到栅极和数据线的薄膜晶体管，像素区域中的像素电极，以及共同的 电极，包括第一，第二，第三，第四和第五部分，其中第一和第二部分设置在数据线的两侧，第三和第四部分中的每一个连接到第一和第二部分，第五部分是 连接到第二部分并且延伸到与像素区域相邻的下一个像素区域。

公开(公告)号：US07833875B2

公开(公告)日：2010-11-16

申请号：US11931571

申请日：2007-10-31

申请人： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

发明人： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC分类号： H01L21/76

CPC分类号： H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

摘要： A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

摘要翻译： 半导体器件包括限定形成在半导体衬底中的有源区的隔离层。 在隔离层上执行第一凹陷处理以暴露活性区域的边缘部分。 执行第一舍入处理以围绕活动区域的边缘部分。 在隔离层上进行第二凹陷处理。 执行第二舍入处理以围绕活动区域的边缘部分。

公开(公告)号：US07766713B2

公开(公告)日：2010-08-03

申请号：US11918221

申请日：2006-02-03

申请人： Byeong-Soo Bae ,  Jung-Hwan Kim ,  Ji-Hoon Ko ,  Kyung-Ho Jung

发明人： Byeong-Soo Bae ,  Jung-Hwan Kim ,  Ji-Hoon Ko ,  Kyung-Ho Jung

IPC分类号： H01J17/49

CPC分类号： H01J9/242 ,  H01J2211/36

摘要： Disclosed herein is a method of manufacturing a barrier rib for a plasma display panel, including a silicon compound resin. The method according to a first embodiment of this invention includes providing a silicon compound resin layer on a substrate; pressing the silicon compound resin layer using a master having a pattern corresponding to the shape of a barrier rib to be transferred; and curing the silicon compound resin and then releasing the master. In addition, the method according to a second embodiment includes loading a silicon compound resin into grooves of a master having a pattern corresponding to the shape of a barrier rib; pressing the master on a substrate to transfer the silicon compound to the substrate; and curing the transferred silicon compound resin and then releasing the master.

摘要翻译： 本文公开了一种制造包括硅化合物树脂的等离子体显示面板的隔壁的方法。 根据本发明的第一实施方案的方法包括在基材上提供硅化合物树脂层; 使用具有对应于要传送的障壁的形状的图案的主体来压制硅化合物树脂层; 并固化硅化合物树脂，然后释放母料。 此外，根据第二实施例的方法包括将硅化合物树脂加载到具有对应于障壁形状的图案的母版的凹槽中; 将基板压在基板上以将硅化合物转印到基板上; 并固化转移的硅化合物树脂，然后释放母料。

公开(公告)号：US20100184636A1

公开(公告)日：2010-07-22

申请号：US12374262

申请日：2007-08-03

申请人： Sung-Ho Ryu ,  Pann-Ghill Suh ,  Sang-Hoon Ha ,  Do-Hyung Kim ,  Il-Shin Kim ,  Jung-Hwan Kim ,  Mi-Nam Lee ,  Hyun-Ju Lee ,  Jong-Heon Kim ,  Sung-Key Jang ,  Tae-Hoon Lee

发明人： Sung-Ho Ryu ,  Pann-Ghill Suh ,  Sang-Hoon Ha ,  Do-Hyung Kim ,  Il-Shin Kim ,  Jung-Hwan Kim ,  Mi-Nam Lee ,  Hyun-Ju Lee ,  Jong-Heon Kim ,  Sung-Key Jang ,  Tae-Hoon Lee

IPC分类号： A61K38/02 ,  A61P35/00 ,  A61P3/04 ,  A61P3/10 ,  C07K2/00 ,  C12Q1/02

CPC分类号： A61K38/1709 ,  C07K14/4702 ,  C12N9/20 ,  C12Y301/04004 ,  G01N33/5011 ,  G01N2333/9121 ,  G01N2333/916

摘要： The present invention relates to a method of regulating mammalian target-of-rapamycin (mTOR) by regulating a phospholipase D (PLD) activity that generates a complex with mTOR. Further, the present invention also relates to a method of screening inhibitors of mTOR, and a method and a composition for treating mTOR-related metabolic diseases by inhibiting mTOR.

摘要翻译： 本发明涉及通过调节与mTOR产生复合物的磷脂酶D（PLD）活性来调节哺乳动物雷帕霉素靶（mTOR）的方法。 此外，本发明还涉及一种筛选mTOR抑制剂的方法，以及通过抑制mTOR来治疗mTOR相关代谢疾病的方法和组合物。

公开(公告)号：US20100117181A1

公开(公告)日：2010-05-13

申请号：US12617910

申请日：2009-11-13

申请人： Jung-Hwan Kim ,  Un-Byoung Kang ,  Dong-Hun Yi ,  Woonseong Kwon ,  Hyung-Sun Jang ,  Jongkeun Jeon ,  Yongjin Lee ,  Keeseok Kim

发明人： Jung-Hwan Kim ,  Un-Byoung Kang ,  Dong-Hun Yi ,  Woonseong Kwon ,  Hyung-Sun Jang ,  Jongkeun Jeon ,  Yongjin Lee ,  Keeseok Kim

IPC分类号： H01L31/0232 ,  H01L31/02

CPC分类号： H01L27/14618 ,  H01L27/14627 ,  H01L27/14632 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/13 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/05099

摘要： Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package includes a semiconductor chip, a transparent substrate, an adhesive pattern, and at least one dew-proofer. The semiconductor includes a pixel area. The transparent substrate is disposed on the semiconductor chip. The adhesive pattern is disposed between the semiconductor chip and the transparent substrate and provides a space on the pixel area. At least one dew-proofer is disposed between the semiconductor chip and the transparent substrate and spaced from the adhesive pattern.

摘要翻译： 提供半导体封装及其制造方法。 半导体封装包括半导体芯片，透明基板，粘合剂图案和至少一个露水开发器。 半导体包括像素区域。 透明基板设置在半导体芯片上。 粘合剂图案设置在半导体芯片和透明基板之间，并且在像素区域上提供空间。 在半导体芯片和透明基板之间设置至少一个露水器，并且与粘合剂图案间隔开。

公开(公告)号：US20070010068A1

公开(公告)日：2007-01-11

申请号：US11481928

申请日：2006-07-07

申请人： Yong-Sun Lee ,  Jai-Dong Lee ,  Bong-Hyun Kim ,  Man-Sug Kang ,  Jung-Hwan Kim ,  Hyun-Jin Shin ,  Won-Seok Yoo ,  Seung-Mok Shin

发明人： Yong-Sun Lee ,  Jai-Dong Lee ,  Bong-Hyun Kim ,  Man-Sug Kang ,  Jung-Hwan Kim ,  Hyun-Jin Shin ,  Won-Seok Yoo ,  Seung-Mok Shin

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/32105 ,  H01L21/28273 ,  H01L29/42324

摘要： Example embodiments of the present invention relate to methods of manufacturing a semiconductor device. Other example embodiments of the present invention relate to methods of manufacturing a semiconductor device having a gate electrode. In the method of manufacturing the semiconductor device, a gate electrode may be formed on a semiconductor substrate. Damage in the semiconductor substrate and a sidewall of the gate electrode may be cured, or repaired, by a radical re-oxidation process to form an oxide layer on the semiconductor substrate and the gate electrode. The radical re-oxidation process may be performed by providing a nitrogen gas onto the semiconductor substrate while increasing a temperature of the semiconductor substrate to a first temperature to passivate a surface of the gate electrode under a nitrogen gas atmosphere, providing an oxygen gas onto the semiconductor substrate while increasing the temperature from a first temperature to a second temperature to perform a first oxidation process and/or performing a second oxidation process at the second temperature.

摘要翻译： 本发明的示例性实施例涉及制造半导体器件的方法。 本发明的其它示例实施例涉及制造具有栅电极的半导体器件的方法。 在制造半导体器件的方法中，可以在半导体衬底上形成栅电极。 可以通过自由基再氧化工艺固化或修复半导体衬底和栅电极的侧壁的损伤，以在半导体衬底和栅电极上形成氧化物层。 可以通过在半导体衬底上提供氮气同时将半导体衬底的温度提高到第一温度以在氮气气氛下钝化栅电极的表面来进行自由基再氧化工艺，从而将氧气提供到 半导体衬底，同时将温度从第一温度升至第二温度，以进行第一氧化工艺和/或在第二温度下进行第二氧化工艺。