公开(公告)号：US20170287696A1

公开(公告)日：2017-10-05

申请号：US15511831

申请日：2014-09-19

Applicant: HITACHI KOKUSAI ELECTRIC INC.

Inventor： Takaaki NODA ,  Shingo NOHARA ,  Kosuke TAKAGI ,  Takeo HANASHIMA ,  Mamoru SUEYOSHI ,  Kotaro KONNO ,  Motoshi SAWADA

IPC: H01L21/02 ,  C23C16/458 ,  C23C16/40

CPC classification number: H01L21/0228 ,  C23C16/401 ,  C23C16/402 ,  C23C16/4408 ,  C23C16/4412 ,  C23C16/452 ,  C23C16/455 ,  C23C16/45512 ,  C23C16/45527 ,  C23C16/45542 ,  C23C16/45544 ,  C23C16/45578 ,  C23C16/4583 ,  C23C16/4587 ,  C23C16/52 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274

Abstract: A semiconductor device manufacturing method includes: vertically arranging and storing a plurality of substrates in a processing container and forming a condition where at least an upper region or a lower region relative to a substrate disposing region where the plurality of substrates are arranged is blocked off by an adaptor; and while maintaining the condition, forming films on the plurality of substrates by performing a cycle including the following steps a predetermined number of times in a non-simultaneous manner: supplying source gas to the plurality of substrates in the processing container from the side of the substrate disposing region; discharging the source gas from the interior of the processing container via exhaust piping; supplying reaction gas to the plurality of substrates in the processing container from the side of the substrate disposing region; and discharging the reaction gas from the interior of the processing container via the exhaust piping.

公开(公告)号：US20170263715A1

公开(公告)日：2017-09-14

申请号：US15067540

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Sudharshanan Raghunathan ,  Andy Chi-Hung Wei ,  Jason Eugene Stephens ,  Vikrant Kumar Chauhan ,  David Michael Permana

IPC: H01L29/40 ,  H01L29/66 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/027 ,  H01L29/49 ,  H01L21/311

CPC classification number: H01L29/401 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0273 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized.

公开(公告)号：US20170256486A1

公开(公告)日：2017-09-07

申请号：US15601562

申请日：2017-05-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yung-Hsu Wu ,  Hai-Ching Chen ,  Jung-Hsun Tsai ,  Shau-Lin Shue ,  Tien-I Bao

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/311 ,  H01L21/033 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/532

Abstract: A first conductive element is disposed. in a first dielectric layer. An etching stop layer is disposed on the first dielectric layer but not on the first conductive element. A first metal capping layer segment is disposed on the first conductive element but not on the first dielectric layer. The etching stop layer has a greater thickness than the first metal capping layer segment. A first segment of a second conductive element is disposed on the first metal capping layer segment. A second segment of the second conductive element is disposed over the first segment of the second conductive element and partially over the etching stop layer. A third conductive element is disposed over the second conductive element.

公开(公告)号：US09735108B2

公开(公告)日：2017-08-15

申请号：US14704096

申请日：2015-05-05

Applicant: Dai Nippon Printing Co., Ltd.

Inventor： Hiroshi Kudo ,  Takamasa Takano

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/02063 ,  H01L21/02071 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/31058 ,  H01L21/31116 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/49822 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H05K1/0231 ,  H05K3/4679 ,  H05K3/4688 ,  H05K2201/068 ,  H01L2924/00

Abstract: A multi-layer line structure including a substrate, a lower layer Cu line located on the substrate, an upper layer Cu line located on an insulating layer including an inorganic film located on the lower layer Cu line and an organic resin film located on the inorganic film, and a via connection part located in a via connection hole running in an up-down direction through the insulating layer in an area where the lower layer Cu line and the upper layer Cu line overlap each other is provided. The via connection part includes a barrier conductive layer located on a part of the lower layer Cu line exposed to a bottom part of the via connection hole and on an inner wall of the via connection hole.

公开(公告)号：US09721897B1

公开(公告)日：2017-08-01

申请号：US15276985

申请日：2016-09-27

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Xin Miao ,  Peng Xu ,  Chen Zhang

IPC: H01L21/768 ,  H01L29/06 ,  H01L23/535 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L29/4991 ,  H01L21/02126 ,  H01L21/28247 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

Abstract: A method of fabricating a semiconductor transistor and the semiconductor transistor include a source region and a drain region within a substrate. The method includes forming a gate above the substrate, forming a source contact above the source region and a drain contact above the drain region, and forming air spacers within a dielectric between the gate and each of the source contact and the drain contact. Metal caps are formed on the source contact and the drain contact, and a gate cap is formed between the dielectric and at least a portion of a bottom surface of higher-level contacts, which are contacts formed above the source contact and the drain contact.

公开(公告)号：US20170213726A1

公开(公告)日：2017-07-27

申请号：US15413956

申请日：2017-01-24

Applicant: Applied Materials, Inc.

Inventor： Mark Saly ,  Bhaskar Jyoti Bhuyan ,  Jeffrey W. Anthis ,  Feng Q. Liu ,  David Thompson

IPC: H01L21/02 ,  C23C16/30 ,  C23C16/32 ,  C23C16/34 ,  C23C16/455 ,  C23C16/40

CPC classification number: H01L21/02208 ,  C23C16/308 ,  C23C16/325 ,  C23C16/345 ,  C23C16/36 ,  C23C16/401 ,  C23C16/402 ,  C23C16/45531 ,  C23C16/45536 ,  C23C16/45542 ,  C23C16/45553 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02142 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/0262

Abstract: Provided are acetylide-based compounds and methods of making the same. Also provided are methods of using said compounds in film deposition processes to deposit films comprising silicon. Certain methods comprise exposing a substrate surface to a acetylide-based precursor and a reactant in various combinations.

公开(公告)号：US09716159B1

公开(公告)日：2017-07-25

申请号：US15375045

申请日：2016-12-09

Applicant: Fuji Electric Co., Ltd.

Inventor： Manabu Takei

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/04 ,  H01L21/02 ,  H01L21/311 ,  H01L29/423

CPC classification number: H01L29/66068 ,  H01L21/02057 ,  H01L21/02123 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/0475 ,  H01L21/049 ,  H01L21/28238 ,  H01L21/31111 ,  H01L21/32 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66053 ,  H01L29/66734 ,  H01L29/7397

Abstract: After a trench is formed, a deposition film is formed on the front surface of a base material and an inner wall of the trench such that a thickness of a portion of the deposition film covering the front surface of the base material is greater than a thickness of a portion of the deposition film covering the inner wall of the trench. The total thickness of the deposition film is then reduced until the inner wall of the trench is exposed, leaving only the portion of the deposition film covering the front surface of the base material. By performing sacrificial oxidation in this state, the thermal oxide film caused by thermal oxidation barely grows at the interface of the front surface of the base material and the deposition film, and thus the thickness of an n+ source region is mostly maintained.

公开(公告)号：US09716007B2

公开(公告)日：2017-07-25

申请号：US15233630

申请日：2016-08-10

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation

Inventor： Zhongshan Hong

IPC: H01L23/52 ,  H01L21/033 ,  H01L21/311 ,  H01L21/02 ,  H01L21/768 ,  H01L21/3213

CPC classification number: H01L21/0338 ,  H01L21/02115 ,  H01L21/02123 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/76816

Abstract: A multiple patterning method is provided. The multiple patterning method includes providing a substrate; and forming a sacrificial film on the substrate. The multiple patterning method also includes forming a first mask film on the sacrificial film; and forming a second mask film for subsequently forming a certain structure to protect the subsequently formed mask structures on the first mask film. Further, the multiple patterning method includes forming first mask structures and second mask structures by etching the second mask film, the first mask film, and the sacrificial film.

公开(公告)号：US20170200805A1

公开(公告)日：2017-07-13

申请号：US15375045

申请日：2016-12-09

Applicant: Fuji Electric Co., Ltd.

Inventor： Manabu TAKEI

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/311 ,  H01L21/04 ,  H01L21/02

CPC classification number: H01L29/66068 ,  H01L21/02057 ,  H01L21/02123 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/0475 ,  H01L21/049 ,  H01L21/28238 ,  H01L21/31111 ,  H01L21/32 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66053 ,  H01L29/66734 ,  H01L29/7397

Abstract: After a trench is formed, a deposition film is formed on the front surface of a base material and an inner wall of the trench such that a thickness of a portion of the deposition film covering the front surface of the base material is greater than a thickness of a portion of the deposition film covering the inner wall of the trench. The total thickness of the deposition film is then reduced until the inner wall of the trench is exposed, leaving only the portion of the deposition film covering the front surface of the base material. By performing sacrificial oxidation in this state, the thermal oxide film caused by thermal oxidation barely grows at the interface of the front surface of the base material and the deposition film, and thus the thickness of an n+ source region is mostly maintained.

公开(公告)号：US09704994B1

公开(公告)日：2017-07-11

申请号：US15289258

申请日：2016-10-10

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Peng Xu ,  Chen Zhang

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/306 ,  H01L29/06 ,  H01L29/51 ,  H01L27/088

CPC classification number: H01L21/76224 ,  H01L21/02126 ,  H01L21/0217 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin field effect transistor (finFET) and a method of fabricating the finFET. The method includes forming one or more fins above a substrate in a channel region, depositing a first insulating material conformally on the one or more fins and the substrate, and depositing a second insulating material over the first insulating material in non-channel regions adjacent to the channel region. A selective etch of the first insulating material in the channel region is performed to form a trench. The trench is filled with the second insulating material. The second insulating material in the channel region is adjacent to the first insulating material in the non-channel regions.