公开(公告)号：US08440564B2

公开(公告)日：2013-05-14

申请号：US13551500

申请日：2012-07-17

申请人： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I Bao

发明人： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： H01L21/44

CPC分类号： H01L23/53238 ,  H01L21/322 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

公开(公告)号：US08433434B2

公开(公告)日：2013-04-30

申请号：US12766626

申请日：2010-04-23

申请人： Amy Wang ,  Chen-Hua Yu ,  Jean Wang ,  Henry Lo ,  Francis Ko ,  Chih-Wei Lai ,  Kewei Zuo

发明人： Amy Wang ,  Chen-Hua Yu ,  Jean Wang ,  Henry Lo ,  Francis Ko ,  Chih-Wei Lai ,  Kewei Zuo

IPC分类号： G06F19/00

CPC分类号： G05B13/048

摘要： Embodiments of the present invention relate to a method for a near non-adaptive virtual metrology for wafer processing control. In accordance with an embodiment of the present invention, a method for processing control comprises diagnosing a chamber of a processing tool that processes a wafer to identify a key chamber parameter, and controlling the chamber based on the key chamber parameter if the key chamber parameter can be controlled, or compensating a prediction model by changing to a secondary prediction model if the key chamber parameter cannot be sufficiently controlled.

摘要翻译： 本发明的实施例涉及一种用于晶片处理控制的近非自适应虚拟测量方法。 根据本发明的实施例，一种用于处理控制的方法包括：诊断处理工具的室，其处理晶片以识别密钥室参数，以及如果密钥室参数可以基于密钥室参数来控制室 如果密钥室参数不能被充分地控制，则通过改变为次级预测模型来控制或补偿预测模型。

公开(公告)号：US08415691B2

公开(公告)日：2013-04-09

申请号：US12202167

申请日：2008-08-29

申请人： Ding-Yuan Chen ,  Chen-Hua Yu ,  Wen-Chih Chiou

发明人： Ding-Yuan Chen ,  Chen-Hua Yu ,  Wen-Chih Chiou

IPC分类号： H01L33/00

CPC分类号： H01L33/60 ,  H01L33/0079 ,  H01L33/10 ,  H01L33/46 ,  H01L2933/0083

摘要： A system and method for manufacturing an LED is provided. A preferred embodiment includes a substrate with a distributed Bragg reflector formed over the substrate. A photonic crystal layer is formed over the distributed Bragg reflector to collimate the light that impinges upon the distributed Bragg reflector, thereby increasing the efficiency of the distributed Bragg reflector. A first contact layer, an active layer, and a second contact layer are preferably either formed over the photonic crystal layer or alternatively attached to the photonic crystal layer.

公开(公告)号：US08399273B2

公开(公告)日：2013-03-19

申请号：US12539757

申请日：2009-08-12

申请人： Ding-Yuan Chen ,  Chen-Hua Yu ,  Wen-Chih Chiou

发明人： Ding-Yuan Chen ,  Chen-Hua Yu ,  Wen-Chih Chiou

IPC分类号： H01L21/00

CPC分类号： H01L33/145 ,  H01L33/0066 ,  H01L33/04 ,  H01L33/06 ,  H01L33/30 ,  H01L33/36 ,  H01L33/62 ,  H01L2933/0066

摘要： A light-emitting diode (LED) device is provided. The LED device has a lower LED layer and an upper LED layer with a light-emitting layer interposed therebetween. A current blocking layer is formed in the upper LED layer such that current passing between an electrode contacting the upper LED layer flows around the current blocking layer. When the current blocking layer is positioned between the electrode and the light-emitting layer, the light emitted by the light-emitting layer is not blocked by the electrode and the light efficiency is increased. The current blocking layer may be formed by converting a portion of the upper LED layer into a resistive region. In an embodiment, ions such as magnesium, carbon, or silicon are implanted into the upper LED layer to form the current blocking layer.

摘要翻译： 提供了一种发光二极管（LED）装置。 LED装置具有较低的LED层和位于其间的发光层的上部LED层。 在上LED层中形成电流阻挡层，使得在与上层LED层接触的电极之间的电流流过电流阻挡层。 当电流阻挡层位于电极和发光层之间时，由发光层发射的光不被电极阻挡，并且光效率增加。 可以通过将上部LED层的一部分转换成电阻区域来形成电流阻挡层。 在一个实施方案中，诸如镁，碳或硅的离子注入上层LED层以形成电流阻挡层。

公开(公告)号：US20130062761A1

公开(公告)日：2013-03-14

申请号：US13228768

申请日：2011-09-09

申请人： Chih-Wei Lin ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Hsiu-Jen Lin ,  Bor-Ping Jang ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu ,  Meng-Tse Chen ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Kuei-Wei Huang ,  Wei-Hung Lin

发明人： Chih-Wei Lin ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Hsiu-Jen Lin ,  Bor-Ping Jang ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu ,  Meng-Tse Chen ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Kuei-Wei Huang ,  Wei-Hung Lin

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L25/0657 ,  H01L21/52 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68377 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06515 ,  H01L2224/09181 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/9202 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15322 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00

摘要： Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.

公开(公告)号：US20130049234A1

公开(公告)日：2013-02-28

申请号：US13216825

申请日：2011-08-24

申请人： Jing-Cheng Lin ,  Chih-Wei Wu ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Jing-Cheng Lin ,  Chih-Wei Wu ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L21/78 ,  H01L23/28

CPC分类号： H01L23/49816 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/97 ,  H01L2224/73204 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method and apparatus for separating a substrate into individual dies and the resulting structure is provided. A modification layer, such as an amorphous layer, is formed within the substrate. A laser focused within the substrate may be used to create the modification layer. The modification layer creates a relatively weaker region that is more prone to cracking than the surrounding substrate material. As a result, the substrate may be pulled apart into separate sections, causing cracks the substrate along the modification layers. Dice or other components may be attached to the substrate before or after separation.

摘要翻译： 提供了一种用于将基底分离成单个模具的方法和装置，并且提供了所得到的结构。 在衬底内形成诸如非晶层的改性层。 可以使用聚焦在衬底内的激光来产生修饰层。 改性层产生比周围的基材更容易破裂的相对较弱的区域。 结果，衬底可以被拉开到分开的部分中，从而沿着修饰层裂开衬底。 在分离之前或之后，骰子或其它组分可附着于基底。

公开(公告)号：US08377816B2

公开(公告)日：2013-02-19

申请号：US12768025

申请日：2010-04-27

申请人： Chung-Shi Liu ,  Shin-Puu Jeng ,  Mirng-Ji Lii ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Shin-Puu Jeng ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC分类号： H01L21/44

CPC分类号： H01L23/3171 ,  H01L21/563 ,  H01L23/525 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/73203 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2224/13099

摘要： A method of forming electrical connections to a semiconductor wafer. A semiconductor wafer comprising an insulation layer is provided. The insulation layer has a surface. A patterned mask layer is formed over the surface of the insulation layer. The patterned mask layer exposes portions of the surface of the insulation layer through a plurality of holes. The portions of the plurality of holes are filled with a metal material comprising copper to form elongated columns of the metal material. The elongated columns of the metal material have a sidewall surface. The patterned mask layer is removed to expose the sidewall surface of the elongated columns of the metal material. A protection layer is formed on the exposed sidewall surface of the elongated columns of the metal material.

摘要翻译： 形成与半导体晶片的电连接的方法。 提供了包括绝缘层的半导体晶片。 绝缘层具有表面。 在绝缘层的表面上形成图案化掩模层。 图案化掩模层通过多个孔暴露绝缘层的表面的部分。 多个孔的部分填充有包含铜的金属材料以形成细长的金属材料柱。 金属材料的细长柱具有侧壁表面。 去除图案化的掩模层以暴露金属材料的细长柱的侧壁表面。 保护层形成在金属材料的细长柱的暴露的侧壁表面上。

公开(公告)号：US20130040423A1

公开(公告)日：2013-02-14

申请号：US13206602

申请日：2011-08-10

申请人： Chih-Hang Tung ,  Chun Hui Yu ,  Chen-Hua Yu ,  Da-Yuan Shih

发明人： Chih-Hang Tung ,  Chun Hui Yu ,  Chen-Hua Yu ,  Da-Yuan Shih

IPC分类号： H01L21/56 ,  H01L21/82

CPC分类号： H01L25/50 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76879 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/19 ,  H01L24/24 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/02311 ,  H01L2224/02381 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/08146 ,  H01L2224/12105 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/03

摘要： A method of multi-chip wafer level packaging comprises forming a reconfigured wafer using a plurality of photo-sensitive material layers. A plurality of semiconductor chips and wafers are embedded in the photo-sensitive material layers. Furthermore, a variety of through assembly vias are formed in the photo-sensitive material layers. Each semiconductor chip embedded in the photo-sensitive material layers is connected to input/output pads through connection paths formed by the through assembly vias.

摘要翻译： 多芯片晶片级封装的方法包括使用多个感光材料层形成重新配置的晶片。 多个半导体芯片和晶片被嵌入到感光材料层中。 此外，在感光材料层中形成各种贯穿组装通孔。 嵌入在感光材料层中的每个半导体芯片通过由通孔组装通孔形成的连接路径连接到输入/输出焊盘。

公开(公告)号：US08344506B2

公开(公告)日：2013-01-01

申请号：US12633499

申请日：2009-12-08

申请人： Cheng-Chung Lin ,  Chung-Shi Liu ,  Chen-Hua Yu

发明人： Cheng-Chung Lin ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L23/50

CPC分类号： H01L21/76885 ,  H01L23/53228 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/81013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2224/05552

摘要： An integrated circuit device is disclosed. An exemplary integrated circuit device includes a first copper layer, a second copper layer, and an interface between the first and second copper layers. The interface includes a flat zone interface region and an intergrowth interface region, wherein the flat zone interface region is less than or equal to 50% of the interface.

摘要翻译： 公开了一种集成电路器件。 示例性的集成电路器件包括第一铜层，第二铜层以及第一和第二铜层之间的界面。 该界面包括平坦区域界面区域和共同生长界面区域，其中平坦区域界面区域小于或等于界面的50％。

公开(公告)号：US08338945B2

公开(公告)日：2012-12-25

申请号：US12953130

申请日：2010-11-23

申请人： Chen-Hua Yu ,  Chun Hui Yu ,  Jing-Cheng Lin

发明人： Chen-Hua Yu ,  Chun Hui Yu ,  Jing-Cheng Lin

IPC分类号： H01L23/48

CPC分类号： H01L25/0655 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3157 ,  H01L23/36 ,  H01L23/42 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/81805

摘要： Apparatus and methods for providing a molded chip interposer structure and assembly. A molded chip structure having at least two integrated circuit dies disposed within a mold compound is provided having the die bond pads on the bottom surface; and solder bumps are formed in the openings of a dielectric layer on the bottom surface, the solder bumps forming connections to the bond pads. An interposer having a die side surface and a board side surface is provided having bump lands receiving the solder bumps of the molded chip structure on the die side of the interposer. An underfill layer is formed between the die side of the interposer and the bottom surface of the molded chip structure surrounding the solder bumps. Methods for forming the molded chip interposer structure are disclosed.

摘要翻译： 用于提供模制芯片插入件结构和组装的装置和方法。 提供具有设置在模具化合物内的至少两个集成电路管芯的模制芯片结构，其具有底表面上的管芯接合焊盘; 并且在底表面上的电介质层的开口中形成焊料凸块，焊料凸块形成与焊盘的连接。 具有裸片侧表面和电路板侧表面的插入件设置有凸起焊盘，其在插入件的裸片侧接收模制芯片结构的焊料凸块。 在插入件的裸片侧和围绕焊料凸块的模制芯片结构的底表面之间形成底部填充层。 公开了用于形成模制芯片内插器结构的方法。