公开(公告)号：US08410618B2

公开(公告)日：2013-04-02

申请号：US13196192

申请日：2011-08-02

申请人： Belgacem Haba ,  Philip Damberg ,  Philip R. Osborn

发明人： Belgacem Haba ,  Philip Damberg ,  Philip R. Osborn

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/49816 ,  H01L21/50 ,  H01L23/13 ,  H01L23/49861 ,  H01L24/01 ,  H01L24/36 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/91 ,  H01L2224/05554 ,  H01L2224/40091 ,  H01L2224/40225 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48096 ,  H01L2224/4813 ,  H01L2224/4824 ,  H01L2224/4846 ,  H01L2224/48465 ,  H01L2224/48477 ,  H01L2224/48599 ,  H01L2224/4911 ,  H01L2224/49112 ,  H01L2224/4942 ,  H01L2224/49427 ,  H01L2224/49429 ,  H01L2224/4945 ,  H01L2224/85051 ,  H01L2224/85191 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19107 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/48095 ,  H01L2224/37099 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A microelectronic assembly includes a semiconductor chip having chip contacts exposed at a first face and a substrate juxtaposed with a face of the chip. A conductive bond element can electrically connect a first chip contact with a first substrate contact of the substrate, and a second conductive bond element can electrically connect the first chip contact with a second substrate contact. The first bond element can have a first end metallurgically joined to the first chip contact and a second end metallurgically joined to the first substrate contact. A first end of the second bond element can be metallurgically joined to the first bond element. The second bond element may or may not touch the first chip contact or the substrate contact. A third bond element can be joined to ends of first and second bond elements which are joined to substrate contacts or to chip contacts. In one embodiment, a bond element can have a looped connection, having first and second ends joined at a first contact and a middle portion joined to a second contact.

摘要翻译： 微电子组件包括半导体芯片，其具有在第一面处露出的芯片触点和与芯片的表面并置的衬底。 导电接合元件可以将第一芯片触点与衬底的第一衬底接触电连接，并且第二导电结合元件可以将第一芯片触点与第二衬底触点电连接。 第一结合元件可以具有冶金地连接到第一芯片触点的第一端和冶金地连接到第一衬底触点的第二端。 第二结合元件的第一端可以冶金地连接到第一结合元件。 第二结合元件可以或可以不接触第一芯片触点或基板触点。 第三接合元件可以连接到第一和第二接合元件的端部，所述第一和第二接合元件连接到衬底触点或芯片触点。 在一个实施例中，接合元件可以具有环形连接，其具有在第一接触处连接的第一端和第二端以及与第二接触接合的中间部。

公开(公告)号：US20130063918A1

公开(公告)日：2013-03-14

申请号：US13232436

申请日：2011-09-14

申请人： Belgacem Haba ,  Kishor Desai

发明人： Belgacem Haba ,  Kishor Desai

IPC分类号： H05K7/00 ,  B32B38/08 ,  H05K1/00 ,  H05K1/11 ,  H05K1/16

CPC分类号： H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/17 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/17104 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4911 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/19107 ,  Y10T29/49128 ,  Y10T428/24521 ,  Y10T428/24802 ,  H01L2924/00 ,  H01L2924/00012

摘要： An interconnection component includes a first support portion has a plurality of first conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent a first surface and a second end adjacent a second surface. A second support portion has a plurality of second conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent the first surface and a second end adjacent the second surface. A redistribution layer is disposed between the second surfaces of the first and second support portions, electrically connecting at least some of the first vias with at least some of the second vias. The first and second support portions can have a coefficient of thermal expansion (“CTE”) of less than 12 parts per million per degree, Celsius (“ppm/° C.”).

摘要翻译： 互连部件包括第一支撑部分，其具有大致垂直于其表面延伸的多个第一导电通孔，使得每个通孔具有邻近第一表面的第一端和邻近第二表面的第二端。 第二支撑部分具有大致垂直于其表面延伸穿过的多个第二导电通路，使得每个通孔具有邻近第一表面的第一端和邻近第二表面的第二端。 再分配层设置在第一和第二支撑部分的第二表面之间，将至少一些第一通孔与至少一些第二通孔电连接。 第一和第二支撑部分的热膨胀系数（CTE）可以低于每百万摄氏度（ppm /℃）的百万分之十二。

公开(公告)号：US08378487B2

公开(公告)日：2013-02-19

申请号：US13356752

申请日：2012-01-24

申请人： Teck-Gyu Kang ,  Belgacem Haba ,  Guilian Gao

发明人： Teck-Gyu Kang ,  Belgacem Haba ,  Guilian Gao

IPC分类号： H01L21/44

CPC分类号： H01L24/16 ,  H01L21/4853 ,  H01L23/3114 ,  H01L23/49811 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L24/81 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/11334 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2224/29099

摘要： Wafer level chip packages including risers having sloped sidewalls and methods of fabricating such chip packages are disclosed. The inventive wafer level chip packages may advantageously be used in various microelectronic assemblies.

摘要翻译： 公开了包括具有倾斜侧壁的立管和制造这种芯片封装的方法的晶片级芯片封装。 本发明的晶片级芯片封装可有利地用于各种微电子组件中。

公开(公告)号：US20120313242A1

公开(公告)日：2012-12-13

申请号：US13155845

申请日：2011-06-08

申请人： Kazuo Sakuma ,  Philip Damberg ,  Belgacem Haba

发明人： Kazuo Sakuma ,  Philip Damberg ,  Belgacem Haba

IPC分类号： H01L23/48 ,  H01L21/60 ,  H01L21/768

CPC分类号： H01L21/4853 ,  H01L23/3142 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/01 ,  H01L24/15 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/2064 ,  H01L2924/20641 ,  H05K1/0284 ,  H05K1/0306 ,  H05K1/09 ,  H05K3/002 ,  H05K2201/0166 ,  H01L2924/00

摘要： An interconnection substrate includes a plurality of electrically conductive elements of at least one wiring layer defining first and second lateral directions. Electrically conductive projections for bonding to electrically conductive contacts of at least one component external to the substrate, extend from the conductive elements above the at least one wiring layer. The conductive projections have end portions remote from the conductive elements and neck portions between the conductive elements and the end portions. The end portions have lower surfaces extending outwardly from the neck portions in at least one of the lateral directions. The substrate further includes a dielectric layer overlying the conductive elements and extending upwardly along the neck portions at least to the lower surfaces. At least portions of the dielectric layer between the conductive projections are recessed below a height of the lower surfaces.

摘要翻译： 互连衬底包括限定第一和第二横向方向的至少一个布线层的多个导电元件。 导电突起，用于粘合到基板外部的至少一个部件的导电触点，从导电元件延伸到至少一个布线层之上。 导电突起具有远离导电元件的端部和导电元件与端部之间的颈部。 端部具有在至少一个横向方向上从颈部部分向外延伸的下表面。 衬底还包括覆盖导电元件并且沿着颈部部分至少向下表面向上延伸的电介质层。 导电突起之间的电介质层的至少部分凹陷在下表面的高度之下。

公开(公告)号：US20120313238A1

公开(公告)日：2012-12-13

申请号：US13155552

申请日：2011-06-08

申请人： Hiroaki Sato ,  Yukio Hashimoto ,  Yoshikuni Nakadaira ,  Norihito Masuda ,  Belgacem Haba ,  Ilyas Mohammed ,  Philip Damberg

发明人： Hiroaki Sato ,  Yukio Hashimoto ,  Yoshikuni Nakadaira ,  Norihito Masuda ,  Belgacem Haba ,  Ilyas Mohammed ,  Philip Damberg

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L21/561 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00

摘要： A microelectronic assembly may include a substrate containing a dielectric element having first and second opposed surfaces. The dielectric element may include a first dielectric layer adjacent the first surface, and a second dielectric layer disposed between the first dielectric layer and the second surface. A Young's modulus of the first dielectric layer may be at least 50% greater than the Young's modulus of the second dielectric layer, which is less than two gigapascal (GPa). A conductive structure may extend through the first and second dielectric layers and electrically connect substrate contacts at the first surface with terminals at the second surface. The substrate contacts may be joined with contacts of a microelectronic element through conductive masses, and a rigid underfill may be between the microelectronic element and the first surface. The terminals may be usable to bond the microelectronic assembly to contacts of a component external to the microelectronic assembly.

摘要翻译： 微电子组件可以包括含有具有第一和第二相对表面的电介质元件的衬底。 电介质元件可以包括与第一表面相邻的第一电介质层，以及设置在第一介电层和第二表面之间的第二电介质层。 第一电介质层的杨氏模量可以比第二电介质层的杨氏模量大至少50％，小于二千兆帕（GPa）。 导电结构可以延伸穿过第一和第二电介质层，并且将第一表面处的基板触点与第二表面上的端子电连接。 衬底触点可以通过导电块与微电子元件的触点接合，并且刚性底部填充可以在微电子元件和第一表面之间。 端子可以用于将微电子组件接合到微电子组件外部的部件的触点。

公开(公告)号：US20120267751A1

公开(公告)日：2012-10-25

申请号：US13091800

申请日：2011-04-21

申请人： Belgacem Haba ,  Ilyas Mohammed

发明人： Belgacem Haba ,  Ilyas Mohammed

IPC分类号： H01L23/482 ,  H01L27/02 ,  H01L21/28

CPC分类号： H01L21/486 ,  H01L23/49827 ,  H01L23/49861 ,  H01L23/49894 ,  H01L2224/16225 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K3/4046 ,  H05K2201/0979 ,  H05K2201/10378 ,  H05K2201/10674

摘要： A method for making an interconnection component is disclosed, including forming a plurality of metal posts extending away from a reference surface. Each post is formed having a pair of opposed end surface and an edge surface extending therebetween. A dielectric layer is formed contacting the edge surfaces and filling spaces between adjacent ones of the posts. The dielectric layer has first and second opposed surfaces adjacent the first and second end surfaces. The dielectric layer has a coefficient of thermal expansion of less than 8 ppm/° C. The interconnection component is completed such that it has no interconnects between the first and second end surfaces of the posts that extend in a lateral direction. First and second pluralities of wettable contacts are adjacent the first and second opposed surfaces. The wettable contacts are usable to bond the interconnection component to a microelectronic element or a circuit panel.

摘要翻译： 公开了一种用于制造互连部件的方法，包括形成远离参考表面延伸的多个金属柱。 每个柱形成具有一对相对的端面和在它们之间延伸的边缘表面。 形成接触边缘表面和相邻柱之间的填充空间的电介质层。 电介质层具有邻近第一和第二端面的第一和第二相对表面。 电介质层的热膨胀系数小于8ppm /℃。互连部件完成，使得它们在横向方向上延伸的柱的第一和第二端面之间没有互连。 第一和第二多个可湿接触部分邻近第一和第二相对表面。 可湿接触可用于将互连部件连接到微电子元件或电路板。

公开(公告)号：US08278764B1

公开(公告)日：2012-10-02

申请号：US13354772

申请日：2012-01-20

申请人： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

发明人： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L25/105 ,  H01L23/13 ,  H01L23/3128 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00

摘要： A microelectronic package can include a substrate having first, second, and third apertures extending between first and second surfaces thereof, first, second, and third microelectronic elements each having a surface facing the first surface, and a plurality of terminals exposed at a central region of the second surface. The apertures can have first, second, and third axes extending in directions of the lengths of the respective apertures. The first and second axes can be parallel to one another. The third axis can be transverse to the first axis. The central region of the second surface of the substrate can be disposed between the first and second axes. The terminals can be configured to carry sufficient address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within at least one of the microelectronic elements.

摘要翻译： 微电子封装可以包括具有在其第一和第二表面之间延伸的第一，第二和第三孔的衬底，每个具有面向第一表面的表面的第一，第二和第三微电子元件，以及暴露在中心区域处的多个端子 的第二个表面。 孔可以具有在相应孔的长度方向上延伸的第一，第二和第三轴。 第一和第二轴线可以彼此平行。 第三轴线可以横向于第一轴线。 基板的第二表面的中心区域可以设置在第一和第二轴线之间。 终端可被配置为承载可用于封装内的电路的足够的地址信息，以从至少一个微电子元件内的存储器存储阵列的所有可寻址的存储单元中确定可寻址的存储器位置。

公开(公告)号：US08241959B2

公开(公告)日：2012-08-14

申请号：US12829709

申请日：2010-07-02

申请人： Belgacem Haba ,  Giles Humpston

发明人： Belgacem Haba ,  Giles Humpston

IPC分类号： H01L21/00

CPC分类号： H01L23/525 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/11 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/85399

摘要： A method of making microelectronic packages includes making a subassembly by providing a plate having a top surface, a bottom surface and openings extending between the top and bottom surfaces, attaching a compliant layer to the top surface of the plate, the compliant layer having openings that are aligned with the openings extending through the plate, and providing electrically conductive features on the compliant layer. After making the subassembly, the bottom surface of the plate is attached with the top surface of a semiconductor wafer so that the openings extending through the plate are aligned with contacts on the wafer. At least some of the electrically conductive features on the compliant layer are electrically interconnected with the contacts on the semiconductor wafer.

摘要翻译： 制造微电子封装的方法包括通过提供具有顶表面，底表面和在顶表面和底表面之间延伸的开口的板来制造子组件，将柔性层附接到板的顶表面，顺应层具有开口， 与延伸穿过板的开口对齐，并且在柔性层上提供导电特征。 在制造子组件之后，板的底表面与半导体晶片的顶表面相连，使得延伸穿过该板的开口与晶片上的触点对准。 柔性层上的至少一些导电特征与半导体晶片上的触点电互连。

公开(公告)号：US08207604B2

公开(公告)日：2012-06-26

申请号：US10985126

申请日：2004-11-10

申请人： Belgacem Haba ,  Masud Beroz ,  Giles Humpston ,  Jae M. Park

发明人： Belgacem Haba ,  Masud Beroz ,  Giles Humpston ,  Jae M. Park

IPC分类号： H01L23/485

CPC分类号： H01L23/13 ,  H01L21/4846 ,  H01L2924/0002 ,  H01R13/2414 ,  H01R13/2464 ,  H01L2924/00

摘要： A microelectronic package includes a mounting structure, a microelectronic element associated with the mounting structure, and a plurality of conductive posts physically connected to the mounting structure and electrically connected to the microelectronic element. The conductive posts project from the mounting structure in an upward direction, at least one of the conductive posts being an offset post. Each offset post has a base connected to the mounting structure, the base of each offset post defining a centroid. Each offset post also defines an upper extremity having a centroid, the centroid of the upper extremity being offset from the centroid of the base in a horizontal offset direction transverse to the upward direction. The mounting structure is adapted to permit tilting of each offset post about a horizontal axis so that the upper extremities may wipe across a contact pad of an opposing circuit board.

摘要翻译： 微电子封装包括安装结构，与安装结构相关联的微电子元件以及物理连接到安装结构并电连接到微电子元件的多个导电柱。 导电柱从安装结构沿向上的方向突出，至少一个导电柱是偏移柱。 每个偏移柱具有连接到安装结构的基座，每个偏置柱的基部限定质心。 每个偏移柱还限定具有质心的上肢，上肢的质心在垂直于向上方向的水平偏移方向上偏离基部的质心。 安装结构适于允许每个偏移柱绕水平轴线倾斜，使得上端部可以擦过相对电路板的接触垫。

公开(公告)号：US20120155055A1

公开(公告)日：2012-06-21

申请号：US13157722

申请日：2011-06-10

申请人： Teck-Gyu Kang ,  Wei-Shun Wang ,  Hiroaki Sato ,  Kiyoaki Hashimoto ,  Yoshikuni Nakadaira ,  Norihito Masuda ,  Belgacem Haba ,  Ilyas Mohammed ,  Philip Damberg

发明人： Teck-Gyu Kang ,  Wei-Shun Wang ,  Hiroaki Sato ,  Kiyoaki Hashimoto ,  Yoshikuni Nakadaira ,  Norihito Masuda ,  Belgacem Haba ,  Ilyas Mohammed ,  Philip Damberg

IPC分类号： H05K7/00 ,  H05K3/36 ,  H05K3/32

CPC分类号： H01L24/81 ,  B23K1/0016 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/133 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/8138 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/831 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/351 ,  H05K1/113 ,  H05K3/341 ,  H05K3/4007 ,  H05K2201/0195 ,  Y10T29/49126 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00014

摘要： A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.

摘要翻译： 微电子组件可以包括包括具有导电元件的刚性介电层的基板，具有在其表面暴露的多个触点的微电子元件以及延伸穿过刚性介电层上的柔性介电层的导电通孔。 通孔将基板触点分别电连接到导电元件，并且基板触点分别连接到微电子元件的触点。 通孔，柔性层和衬底触点适于明显地减轻与组件的差分热接触和膨胀相关联的衬底触点处的应力。