公开(公告)号：US08586465B2

公开(公告)日：2013-11-19

申请号：US12133376

申请日：2008-06-05

申请人： Hao Liu ,  Yi Sheng Anthony Sun ,  Ravi Kanth Kolan ,  Chin Hock Toh

发明人： Hao Liu ,  Yi Sheng Anthony Sun ,  Ravi Kanth Kolan ,  Chin Hock Toh

IPC分类号： H01L21/768

CPC分类号： H01L24/80 ,  H01L21/768 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68377 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16237 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask includes mask openings that expose the vias. The mask openings are filled with a conductive material. The method includes reflowing to at least partially fill the vias and contact openings to form via contacts in the vias and surface contacts in the mask openings.

摘要翻译： 公开了一种用于制造包装用模具的方法。 提供具有第一和第二主表面的模具。 在模具的第一主表面上形成通孔和掩模层。 掩模包括露出通孔的掩模开口。 掩模开口用导电材料填充。 该方法包括回流以至少部分地填充通孔和接触开口，以在掩模开口中的通孔和表面接触中形成通孔接触。

公开(公告)号：US08384203B2

公开(公告)日：2013-02-26

申请号：US12505552

申请日：2009-07-20

申请人： Chin Hock Toh ,  Yi Sheng Anthony Sun ,  Xue Ren Zhang ,  Ravi Kanth Kolan

发明人： Chin Hock Toh ,  Yi Sheng Anthony Sun ,  Xue Ren Zhang ,  Ravi Kanth Kolan

IPC分类号： H01L23/48 ,  H01L21/00

CPC分类号： H01L21/568 ,  H01L21/50 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24227 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00

摘要： A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate.

公开(公告)号：US20090236726A1

公开(公告)日：2009-09-24

申请号：US12333328

申请日：2008-12-12

申请人： Danny RETUTA ,  Hien Boon TAN ,  Yi Sheng Anthony SUN ,  Librado Amurao GATBONTON ,  Antonio DIMAANO, JR.

发明人： Danny RETUTA ,  Hien Boon TAN ,  Yi Sheng Anthony SUN ,  Librado Amurao GATBONTON ,  Antonio DIMAANO, JR.

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L23/13 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package that includes a substrate having first and second major surfaces is presented. The package includes a plurality of landing pads and a semiconductor die disposed on the first major surface. A molded cap is disposed on the first surface to encapsulate the die and substrate. The landing pads are covered when the cap is molded. Package interconnects are coupled to the landing pads. The package interconnects are exposed by the cap to facilitate package stacking.

摘要翻译： 提供了包括具有第一和第二主表面的基板的半导体封装。 封装包括多个着陆焊盘和设置在第一主表面上的半导体管芯。 模制帽设置在第一表面上以封装模具和基底。 当盖被模制时，着陆垫被覆盖。 封装互连耦合到着陆焊盘。 封装互连由盖子暴露以便于封装堆叠。

公开(公告)号：US07851899B2

公开(公告)日：2010-12-14

申请号：US10552046

申请日：2004-04-02

申请人： Fung Leng Chen ,  Seong Kwang Brandon Kim ,  Wee Lim Cha ,  Yi-Sheng Anthony Sun ,  Wolfgang Hetzel ,  Jochen Thomas

发明人： Fung Leng Chen ,  Seong Kwang Brandon Kim ,  Wee Lim Cha ,  Yi-Sheng Anthony Sun ,  Wolfgang Hetzel ,  Jochen Thomas

IPC分类号： H01L23/02 ,  H01L23/12 ,  H01L23/00

CPC分类号： H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L25/105 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/85 ,  H01L2224/92147 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1094 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A BGA package is disclosed including a base IC structure having a base substrate, with an opening running length-wise there through. A first semiconductor chip is mounted face-down on the base substrate so the bond pads thereof are accessible through the opening. The package also includes a secondary IC structure including a secondary substrate, having an opening running there through, and a second semiconductor chip. The second chip is mounted face-down on the secondary substrate so that the bond pads thereof are accessible through the opening in the secondary substrate. An encapsulant fills the opening in the secondary substrate and forms a substantially planar surface over the underside of the secondary substrate. The substantially planar surface is mounted to the first chip of the base IC structure through an adhesive. Wires connect a conductive portion of the secondary IC structure to a conductive portion of the base IC structure.

摘要翻译： 公开了一种BGA封装，其包括具有基底基板的基底IC结构，其开口沿着贯穿的方向延伸。 第一半导体芯片正面朝下地安装在基底基板上，使得其接合焊盘可通过开口接近。 该封装还包括一个次级IC结构，该二级IC结构包括一个具有在其上延伸的开口的次级衬底和一个第二半导体芯片。 第二芯片正面朝下安装在二次基板上，使得其接合焊盘可通过次级基板中的开口接近。 密封剂填充次级基底中的开口并且在次级基底的下侧上形成基本平坦的表面。 基本平坦的表面通过粘合剂安装到基底IC结构的第一芯片上。 导线将次级IC结构的导电部分连接到基极IC结构的导电部分。

公开(公告)号：US08772921B2

公开(公告)日：2014-07-08

申请号：US13347683

申请日：2012-01-10

申请人： Chin Hock Toh ,  Yao Huang Huang ,  Ravi Kanth Kolan ,  Wei Liang Yuan ,  Susanto Tanary ,  Yi Sheng Anthony Sun

发明人： Chin Hock Toh ,  Yao Huang Huang ,  Ravi Kanth Kolan ,  Wei Liang Yuan ,  Susanto Tanary ,  Yi Sheng Anthony Sun

IPC分类号： H01L23/02

CPC分类号： H01L21/563 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H05K3/3478 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09572 ,  H05K2201/10378 ,  H05K2203/043 ,  Y10T29/49155 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

摘要： An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact.

摘要翻译： 介绍了插件。 插入器包括具有第一和第二表面的插入器基座。 再分配层设置在插入器基座的第一表面上。 插入器具有耦合到再分配层的至少一个插入器焊盘。 它还包括在第二表面上的至少一个中介层接触。 插入器触点通过再分配层电耦合到插入器衬垫。 插入器还包括通过插入器基座的至少一个插入器，用于将插入器触点耦合到再分配层。 插入器通孔包括内插器接触件的回流导电材料。

公开(公告)号：US08686543B2

公开(公告)日：2014-04-01

申请号：US13284116

申请日：2011-10-28

申请人： Albert Bergemont ,  Uppili Sridhar ,  Joseph Ellul ,  Yi-Sheng Anthony Sun ,  Elliott Simons

发明人： Albert Bergemont ,  Uppili Sridhar ,  Joseph Ellul ,  Yi-Sheng Anthony Sun ,  Elliott Simons

IPC分类号： H01L23/58 ,  H01L21/50

CPC分类号： H01L23/13 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/167 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01029 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/15153 ,  H01L2924/15321 ,  H01L2924/157 ,  H01L2924/00

摘要： A 3D chip package is disclosed that includes a carrier substrate with a first cavity and a second cavity formed therein. A first structure is attached to the carrier substrate at least partially in the first cavity, and a second structure is attached to the carrier substrate at least partially in the second cavity, where the first and second structures include electrical circuitry. A shield layer may be disposed between the carrier substrate and the first structure and/or the second structure for isolating the first structure and/or the second structure at least one of electrically, magnetically, optically, or thermally. In some embodiments, the shield layer may be a dielectric shield layer for dielectrically coupling the first structure and the second structure. The first structure and the second structure may be homogeneous or heterogeneous.

摘要翻译： 公开了一种3D芯片封装，其包括其中形成有第一腔和第二腔的载体衬底。 第一结构至少部分地附接到载体衬底在第一空腔中，并且第二结构至少部分地附接到载体衬底在第二腔中，其中第一和第二结构包括电路。 可以在载体基板和第一结构和/或第二结构之间设置屏蔽层，用于隔离第一结构和/或第二结构以电，磁，光或热中的至少一个。 在一些实施例中，屏蔽层可以是用于介电耦合第一结构和第二结构的电介质屏蔽层。 第一结构和第二结构可以是均匀的或异质的。

公开(公告)号：US08647924B2

公开(公告)日：2014-02-11

申请号：US12758820

申请日：2010-04-13

申请人： Chin Hock Toh ,  Keng Yuen Au ,  Reynaldo Vincent Hernandez Sta Agueda ,  Bee Liang Catherine Ng ,  Librado Amurao Gatbonton ,  Xue Ren Zhang ,  Yi-Sheng Anthony Sun

发明人： Chin Hock Toh ,  Keng Yuen Au ,  Reynaldo Vincent Hernandez Sta Agueda ,  Bee Liang Catherine Ng ,  Librado Amurao Gatbonton ,  Xue Ren Zhang ,  Yi-Sheng Anthony Sun

IPC分类号： H01L21/00

CPC分类号： H01L24/73 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/056 ,  H01L2224/0612 ,  H01L2224/06136 ,  H01L2224/11334 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48799 ,  H01L2224/73104 ,  H01L2224/73215 ,  H01L2224/81005 ,  H01L2224/81011 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

摘要： A method of forming a device stack is presented. The method includes providing a temporary substrate having a temporary mounting surface. A first chip is temporarily mounted to the temporary mounting surface. A first bottom surface of the first chip is temporarily mounted to the temporary mounting surface and a first top surface of the first chip comprises first interconnects. A second chip is stacked on the first chip. The second chip includes second conductive contacts on the second bottom surface. The method also includes bonding the first and second chips together to form the device stack. The second conductive contacts are coupled to the first interconnects. The first bottom surface of the first chip is separated from the substrate to separate the chip stack from the substrate.

摘要翻译： 提出了一种形成器件堆叠的方法。 该方法包括提供具有临时安装表面的临时衬底。 第一芯片临时安装到临时安装表面。 第一芯片的第一底表面临时安装到临时安装表面，并且第一芯片的第一顶表面包括第一互连。 第二芯片堆叠在第一芯片上。 第二芯片包括在第二底表面上的第二导电触点。 该方法还包括将第一和第二芯片接合在一起以形成器件堆叠。 第二导电触点耦合到第一互连。 第一芯片的第一底表面与衬底分离，以将芯片堆叠与衬底分离。

公开(公告)号：US20120104628A1

公开(公告)日：2012-05-03

申请号：US13347683

申请日：2012-01-10

申请人： Chin Hock TOH ,  Yao Huang HUANG ,  Ravi Kanth KOLAN ,  Wei Liang YUAN ,  Susanto TANARY ,  Yi Sheng Anthony SUN

发明人： Chin Hock TOH ,  Yao Huang HUANG ,  Ravi Kanth KOLAN ,  Wei Liang YUAN ,  Susanto TANARY ,  Yi Sheng Anthony SUN

IPC分类号： H01L23/538 ,  H01L21/768

CPC分类号： H01L21/563 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H05K3/3478 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09572 ,  H05K2201/10378 ,  H05K2203/043 ,  Y10T29/49155 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

摘要： An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact.

摘要翻译： 介绍了插件。 插入器包括具有第一和第二表面的插入器基座。 再分配层设置在插入器基座的第一表面上。 插入器具有耦合到再分配层的至少一个插入器焊盘。 它还包括在第二表面上的至少一个中介层接触。 插入器触点通过再分配层电耦合到插入器衬垫。 插入器还包括通过插入器基座的至少一个插入器，用于将插入器触点耦合到再分配层。 插入器通孔包括内插器接触件的回流导电材料。

公开(公告)号：US20100109142A1

公开(公告)日：2010-05-06

申请号：US12604613

申请日：2009-10-23

申请人： Chin Hock Toh ,  Yao Huang Huang ,  Ravi Kanth Kolan ,  Wei Liang Yuan ,  Susanto Tanary ,  Yi Sheng Anthony Sun

发明人： Chin Hock Toh ,  Yao Huang Huang ,  Ravi Kanth Kolan ,  Wei Liang Yuan ,  Susanto Tanary ,  Yi Sheng Anthony Sun

IPC分类号： H01L23/498 ,  H05K1/11 ,  H05K3/10

CPC分类号： H01L21/563 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H05K3/3478 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09572 ,  H05K2201/10378 ,  H05K2203/043 ,  Y10T29/49155 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

摘要： An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact.

摘要翻译： 介绍了插件。 插入器包括具有第一和第二表面的插入器基座。 再分配层设置在插入器基座的第一表面上。 插入器具有耦合到再分配层的至少一个插入器焊盘。 它还包括在第二表面上的至少一个中介层接触。 插入器触点通过再分配层电耦合到插入器衬垫。 插入器还包括通过插入器基座的至少一个插入器，用于将插入器触点耦合到再分配层。 插入器通孔包括内插器接触件的回流导电材料。

公开(公告)号：US07339278B2

公开(公告)日：2008-03-04

申请号：US11536635

申请日：2006-09-28

申请人： Henry Iksan ,  Seong Kwang Brandon Kim ,  Susanto Tanary ,  Hien Boon Tan ,  Yi Sheng Anthony Sun

发明人： Henry Iksan ,  Seong Kwang Brandon Kim ,  Susanto Tanary ,  Hien Boon Tan ,  Yi Sheng Anthony Sun

IPC分类号： H01L23/48 ,  H01L23/52 ,  H11L29/40

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83051 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A package for an IC includes a carrier with a cavity formed on one of the major surfaces. Bumps of a semiconductor die are mated to contact pads located on the bottom of the cavity. The die is attached to the major surface of the carrier. The major surface creates a support which securely holds the chip in place with adhesive for assembly.

摘要翻译： 用于IC的封装件包括具有形成在其中一个主表面上的空腔的载体。 半导体管芯的撞击件与位于腔体底部的接触焊盘配合。 模具附接到载体的主表面。 主表面形成一个支架，通过粘合剂将芯片牢固地固定在一起。