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1.发明授权公开(公告)号：US07084494B2
公开(公告)日：2006-08-01
申请号：US10871645
申请日：2004-06-18
IPC分类号： H01L23/34
CPC分类号： H01L23/4334 , H01L24/48 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/01078 , H01L2924/14 , H01L2924/16152 , H01L2924/181 , H01L2924/19041 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device comprising a metallic leadframe (103) with a first surface (103a) and a second surface (103b). The leadframe includes a chip pad (104) and a plurality of segments (107); the chip pad is held by a plurality of straps (105), wherein each strap has a groove (106). A chip (101) is mounted on the chip pad and electrically connected to the segments. A heat spreader (110) is disposed on the first surface of the leadframe; the heat spreader has its central portion (110a) spaced above the chip connections (108), and also has positioning members (110b) extending outwardly from the edges of the central portion so that they rest in the grooves of the straps. Encapsulation material surrounds the chip, the electrical connections, and the spreader positioning members, and fills the space between the spreader and the chip, while leaving the second leadframe surface and the central spreader portion exposed.
摘要翻译： 一种半导体器件，包括具有第一表面（103a）和第二表面（103b）的金属引线框架（103）。 引线框架包括芯片焊盘（104）和多个段（107）; 所述芯片垫由多个带（105）保持，其中每个带具有凹槽（106）。 芯片（101）安装在芯片焊盘上并电连接到段上。 散热器（110）设置在引线框架的第一表面上; 散热器具有在芯片连接件（108）上方间隔开的中心部分（110a），并且还具有从中心部分的边缘向外延伸的定位构件（110b），使得它们搁置在带的凹槽中。 封装材料围绕芯片，电连接和扩展器定位构件，并且填充扩展器和芯片之间的空间，同时使第二引线框表面和中心扩展器部分露出。
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公开(公告)号：USRE46466E1
公开(公告)日：2017-07-04
申请号：US12712934
申请日：2010-02-25
IPC分类号： H01L21/82 , H01L21/44 , H01L23/532 , H01L23/00 , H01L23/528 , H01L23/31
CPC分类号： H01L23/53238 , H01L23/3121 , H01L23/3192 , H01L23/528 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L24/94 , H01L2224/02311 , H01L2224/02313 , H01L2224/02331 , H01L2224/0235 , H01L2224/02375 , H01L2224/0239 , H01L2224/0345 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05024 , H01L2224/05073 , H01L2224/05166 , H01L2224/05647 , H01L2224/11462 , H01L2224/1147 , H01L2224/11912 , H01L2224/13013 , H01L2224/13082 , H01L2224/13099 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/14133 , H01L2224/16225 , H01L2224/16245 , H01L2224/81191 , H01L2224/81424 , H01L2224/81447 , H01L2224/8146 , H01L2224/81815 , H01L2224/94 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/181 , H01L2924/19043 , H01L2924/30107 , H01L2924/3841 , H01L2924/00014 , H01L2224/11 , H01L2224/03 , H01L2924/01028 , H01L2224/05193 , H01L2924/013 , H01L2924/00
摘要： A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.
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3.发明申请公开(公告)号：US20080157299A1
公开(公告)日：2008-07-03
申请号：US11617504
申请日：2006-12-28
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L23/4951 , H01L23/3121 , H01L23/49548 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L24/83 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/83 , H01L2924/00014 , H01L2924/07802 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Packaged microelectronic semiconductor devices and methods for their assembly are described. According to preferred embodiments of the invention, chip-on-lead techniques are adapted to provide chip-on-lead packages using cantilevered leads. Exemplary embodiments of the invention include methods using a temporary brace to support the cantilevered leads during chip mounting. Versatile chip package embodiments are disclosed including those in which the chip mounting pad is smaller than the chip(s) mounted thereupon, and further examples wherein the chip mounting pad is dispensed with and a chip is mounted on the cantilevered leads alone.
摘要翻译： 描述了封装的微电子半导体器件及其组装方法。 根据本发明的优选实施例，芯片引线技术适于使用悬臂引线提供芯片上导联封装。 本发明的示例性实施例包括在芯片安装期间使用临时支架来支撑悬臂引线的方法。 公开了通用芯片封装实施例，其包括其中芯片安装焊盘小于其上安装的芯片的实施例，以及其中省去了芯片安装焊盘并且芯片单独安装在悬臂引线上的其它示例。
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公开(公告)号：US20080102563A1
公开(公告)日：2008-05-01
申请号：US11554728
申请日：2006-10-31
IPC分类号： H01L23/495 , H01L21/00
CPC分类号： H01L21/561 , H01L21/4821 , H01L23/3121 , H01L23/49582 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/16245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/97 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , H05K3/341 , H05K2201/10689 , H05K2201/10931 , H05K2201/10969 , H05K2201/10984 , Y02P70/613 , H01L2224/85 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： Disclosed herein is a method of manufacturing a semiconductor package with a solder standoff on lead pads that reach to the edge of the package (non-pullback leads). It includes encapsulating a plurality of die on a lead frame strip. The lead frame strip comprises a plurality of package sites, which further comprises a plurality of lead pads and a die pad. The method also includes forming a channel between the lead pads of nearby package sites without singulating the packages. Another step in the method includes disposing solder on the lead pads, the die pad, or the lead pads and the die pads without substantially covering the channel with solder. The manufacturing method further includes singulating the packages.
摘要翻译： 本文公开了一种制造半导体封装的方法，该半导体封装在引线焊盘上具有焊接位置，该焊盘抵达封装的边缘（非拉回引线）。 它包括将多个管芯封装在引线框架条上。 引线框架条包括多个封装位置，其还包括多个引线焊盘和管芯焊盘。 该方法还包括在附近的封装位置的引线焊盘之间形成通道，而不需要对封装进行分离。 该方法的另一步骤包括在焊盘，芯片焊盘或引线焊盘和裸片焊盘上布置焊料，而基本上不用焊料覆盖焊道。 制造方法还包括将包装分离。
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5.发明授权Flip chip package with advanced electrical and thermal properties for high current designs 有权倒装芯片封装具有先进的电气和热性能，适用于高电流设计公开(公告)号：US07476976B2
公开(公告)日：2009-01-13
申请号：US11358668
申请日：2006-02-21
CPC分类号： H01L23/4334 , H01L23/3107 , H01L23/3121 , H01L23/3677 , H01L23/5286 , H01L24/17 , H01L24/45 , H01L24/48 , H01L2224/05001 , H01L2224/05022 , H01L2224/05567 , H01L2224/05568 , H01L2224/05573 , H01L2224/056 , H01L2224/13099 , H01L2224/16 , H01L2224/45014 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/73253 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/20752 , H01L2924/20753 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/00 , H01L2924/2075 , H01L2924/2076 , H01L2924/20754 , H01L2924/00012 , H01L2224/05099
摘要： A QFN package and method of making same is provided comprising a substrate having a metal line extending from a connection element on a perimeter region of the substrate to a high current contact pad on interior region of the substrate. A semiconductor chip having an active surface generally faces the interior region of the substrate, wherein a heat-dissipating patterned metal distribution layer is formed over the active surface and electrically connected to an active component thereon. A solder strip electrically and thermally connects the high current contact pad and the metal distribution layer, and a mold compound generally encapsulates the semiconductor chip. The solder strip is generally uniform in depth and surface area, wherein low electrical resistance and inductance is provided between the high current contact pad and the metal distribution layer. An integrated heat sink may be further formed or placed on a passive surface of the chip.
摘要翻译： 提供了一种QFN封装及其制造方法，包括：具有从衬底的周边区域上的连接元件延伸到衬底的内部区域上的高电流接触焊盘的金属线的衬底。 具有活性表面的半导体芯片大致面向衬底的内部区域，其中散热图案化的金属分布层形成在活性表面上并与其上的活性组分电连接。 焊接电极电连接高电流接触焊盘和金属分布层，并且模制化合物通常封装半导体芯片。 焊料条的深度和表面积通常是均匀的，其中在高电流接触焊盘和金属分布层之间提供低电阻和电感。 集成散热器可以进一步形成或放置在芯片的被动表面上。
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公开(公告)号：US20070296056A1
公开(公告)日：2007-12-27
申请号：US11426591
申请日：2006-06-27
IPC分类号： H01L29/00
CPC分类号： H01L24/85 , H01F17/0006 , H01F17/02 , H01L23/66 , H01L24/45 , H01L24/48 , H01L2223/6611 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/4809 , H01L2224/48091 , H01L2224/48092 , H01L2224/4813 , H01L2224/48599 , H01L2224/85 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/19042 , H01L2924/19104 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/30107 , H01L2924/00014
摘要： An electronic device has a semiconductor chip (101) with a surface and an electric circuit including terminals on the surface. The circuit has a first (103) and a second terminal (104) with a metallurgical composition for wire bonding. The chip has a conductive wire (120) above the chip surface, which has a length and a first and a second end; the first end is attached to the first terminal and the second end to the second terminal. The wire is shaped to form at least one sequence of a concave and a convex portion. The sequence may be configured to form a loop, or multiple wire loops resulting in a spiraling wire coil. The number, shape, and spatial sequence of the loops control the electrical inductance of the wire; the inductance is selected to fine-tune the high frequency characteristics of the circuit.
摘要翻译： 电子设备具有表面和包括端子在内的电路的半导体芯片（101）。 电路具有用于引线接合的冶金组合物的第一（103）和第二端子（104）。 芯片具有在芯片表面上方的导线（120），其具有长度和第一和第二端; 第一端附接到第一端子，第二端部连接到第二端子。 导线成形为形成至少一个凹部和凸部的序列。 该顺序可以被配置为形成环路，或者多个线环形成螺旋线圈。 回路的数量，形状和空间顺序控制电线的电感; 选择电感来微调电路的高频特性。
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公开(公告)号：US06753616B2
公开(公告)日：2004-06-22
申请号：US10320585
申请日：2002-12-16
申请人： Anthony L. Coyle
发明人： Anthony L. Coyle
IPC分类号： H01L2328
CPC分类号： H01L21/56 , H01L21/561 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L24/97 , H01L2224/05554 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/97 , H01L2924/00014 , H01L2924/00015 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01077 , H01L2924/01082 , H01L2924/01322 , H01L2924/10253 , H01L2924/12044 , H01L2924/14 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2224/81 , H01L2224/83 , H01L2924/00 , H01L2224/85399 , H01L2224/05599 , H01L2224/45099 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A robust, low inductance electronic package for small area semiconductor chips is provided which includes a flexible polymer film having electronic circuitry on one or more major surfaces, a bumped flip chip integrated circuit attached to the first surface, an array of solder balls to the second surface, and the device encapsulated in a plastic molding compound. An assembly and packaging method is disclosed wherein multiple devices are encapsulated simultaneously on a continuous polymer film, thereby providing a method compatible with high volume and low cost manufacturing processes and equipment.
摘要翻译： 提供了一种用于小面积半导体芯片的坚固的低电感电子封装，其包括在一个或多个主表面上具有电子电路的柔性聚合物膜，附接到第一表面的凸起的倒装芯片集成电路，第二个焊球的阵列 表面和封装在塑料模塑料中的装置。 公开了一种组装和包装方法，其中多个装置同时被包封在连续聚合物膜上，从而提供与大量和低成本的制造工艺和设备兼容的方法。
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公开(公告)号：US06696757B2
公开(公告)日：2004-02-24
申请号：US10178138
申请日：2002-06-24
申请人： Mohammad Yunus , Anthony L. Coyle
发明人： Mohammad Yunus , Anthony L. Coyle
IPC分类号： H01L2348
CPC分类号： H01L23/49816 , H01L2924/0002 , H05K1/111 , H05K3/3457 , H05K2201/0373 , Y02P70/611 , H01L2924/00
摘要： A metallurgical interconnection for electronic devices is described, wherein the interconnection has first and second interconnection metals. The first metal is shaped to enlarge the contact area, thus providing maximum mechanical interconnection strength, and to stop nascent cracks, which propagate in the interconnection. Preferred shapes include castellation and corrugation. The castellation may include metal protrusions, which create wall-like obstacles in the interconnection zones of highest thermomechanical stress, whereby propagating cracks are stopped. The surface of the first metal has an affinity to form metallurgical contacts. The second metal is capable of reflowing. The first metal is preferably copper, and the second metal tin or a tin alloy.
摘要翻译： 描述了用于电子设备的冶金互连，其中互连具有第一和第二互连金属。 第一金属被成形为扩大接触面积，从而提供最大的机械互连强度，并且停止在互连中传播的新生裂纹。 优选的形状包括城堡和波纹。 这个城堡可能包括金属突起，它们在最高的热机械应力的互连区域中形成壁状障碍物，从而停止传播裂缝。 第一金属的表面具有形成冶金接触的亲和力。 第二种金属能够回流。 第一金属优选为铜，第二金属锡或锡合金。
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公开(公告)号：US08154117B2
公开(公告)日：2012-04-10
申请号：US12347522
申请日：2008-12-31
IPC分类号： H01L23/488
CPC分类号： H01L24/06 , H01L23/49838 , H01L23/50 , H01L24/05 , H01L2224/0401 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05555 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/09701 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15787 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit (IC) includes a substrate having a semiconducting surface, a first array of devices on and in the semiconducting surface including first and second coacting current conducting nodes, a plurality of layers disposed on the substrate and including at a electrically conductive layers and dielectric layer, and a plurality of bump pads on or in the top surface of the dielectric layers. In the IC, the electrically conductive layers define electrical traces, where a first portion of the electrical traces contact a first portion of the bump pads exclusively to a portion of the first coacting current conducting nodes, where a second portion of the electrical traces contact a second portion of the bump pads exclusively to a portion of the second coacting current conducting nodes, and where the electrical traces are electrically isolated from one another by the dielectric layers.
摘要翻译： 集成电路（IC）包括具有半导体表面的衬底，在半导体表面上和半导体表面中的第一阵列的器件，包括第一和第二共同电流导电节点，多个层，设置在衬底上并且包括导电层和 电介质层，以及介电层顶表面上或其中的多个凸块焊盘。 在IC中，导电层限定电迹线，其中电迹线的第一部分将凸点焊盘的第一部分独占地与第一共同电流传导节点的一部分接触，其中电迹线的第二部分接触 凸块的第二部分专用于第二共同电流传导节点的一部分，并且其中电迹线通过电介质层彼此电隔离。
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公开(公告)号：US20100171201A1
公开(公告)日：2010-07-08
申请号：US12349197
申请日：2009-01-06
CPC分类号： H01L23/49568 , H01L23/49503 , H01L23/49548 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/49171 , H01L2224/49175 , H01L2924/00014 , H01L2924/10253 , Y10T29/49002 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of a semiconductor device and method provide a quad flat no-lead semiconductor package which can have an arrangement of both chip-on-lead (COL) style leads and a die pad for supporting a die, and can also provide non-COL leads, both COL leads and a leadframe power pad, COL leads which have varying lengths to reduce stress resulting from thermal mismatch between a semiconductor die and leads, and a die pad with a curved, meandering edge to reduce stress resulting from thermal mismatch between the semiconductor die and the die pad.
摘要翻译： 半导体器件和方法的实施例提供四引脚扁平无引线半导体封装，其可以具有引线引线（COL）型引线和用于支撑管芯的管芯焊盘的布置，并且还可以提供非COL引线 ，COL引线和引线框功率垫，COL引线，其具有不同的长度以减少由半导体管芯和引线之间的热失配引起的应力，以及具有弯曲的曲折边缘的管芯焊盘，以减少由半导体之间的热失配引起的应力 模具和模具垫。
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