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    Two signal one power plane circuit board
    4.
    发明授权
    Two signal one power plane circuit board 有权
    两个信号一个电源平面电路板

    公开(公告)号：US06204453B1

    公开(公告)日：2001-03-20

    申请号：US09203956

    申请日：1998-12-02

    申请人： Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

    发明人： Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

    IPC分类号： H05K103

    CPC分类号： H05K3/44 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/108 ,  H05K3/426 ,  H05K3/445 ,  H05K2201/09554 ,  H05K2203/0733

    摘要： A method of forming a printed circuit board or circuit card is provided with a metal layer which serves as a power plane sandwiched between a pair of photoimageable dielectric layers. Photoformed metal filled vias and photoformed plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials and connected to the vias and plated through holes. A border may be around the board or card including a metal layer terminating in from the edge of one of the dielectric layers. A copper foil is provided with clearance holes. First and second layers of photoimageable curable dielectric material is disposed on opposite sides of the copper which are photoimageable material. The patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. At the clearance holes in the copper, through holes are developed where holes were patterned in both dielectric layers. Thereafter, the surfaces of the photoimageable material, vias and through holes are metalized by copper plating. This is preferably done by protecting the remainder of the circuitry with photoresist and utilizing photolithographic techniques. The photoresist is thereafter removed, leaving a circuit board or card having metalization on both sides, vias extending from both sides to the copper layer in the center, plated through holes connecting the two outer circuitized copper layers.

    摘要翻译： 形成印刷电路板或电路卡的方法设置有用作夹在一对可光成像的电介质层之间的电力平面的金属层。 光刻图形金属填充的通孔和光成像的电镀通孔位于光图案化材料中，信号电路位于每个介电材料的表面上，并连接到通孔和电镀通孔。 边界可以在板或卡周围，包括从电介质层之一的边缘终止的金属层。 铜箔上设有间隙孔。 可光成像的可固化介电材料的第一和第二层设置在作为可光成像的材料的铜的相对侧上。 图案在可光成象材料的第一层和第二层上显影，以通过通孔显露金属层。 在铜中的间隙孔处，通孔被开发成在两个电介质层中图案化孔。 此后，可光成像材料，通孔和通孔的表面通过镀铜进行金属化。 这优选通过用光致抗蚀剂和利用光刻技术保护电路的其余部分来实现。 然后去除光致抗蚀剂，留下在两侧具有金属化的电路板或卡，其中心的两侧延伸到铜层，通孔连接两个外部电路化的铜层。

    Method of forming a capacitive element
    6.
    发明授权
    Method of forming a capacitive element 失效
    形成电容元件的方法

    公开(公告)号：US06625857B2

    公开(公告)日：2003-09-30

    申请号：US09773998

    申请日：2001-02-01

    申请人： Bernd K. Appelt ,  John M. Lauffer

    发明人： Bernd K. Appelt ,  John M. Lauffer

    IPC分类号： H01G700

    CPC分类号： H05K1/162 ,  H05K1/0366 ,  H05K3/429 ,  H05K3/4641 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/09309 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/5102

    摘要： A method of forming a capacitive element for a circuit board or chip carrier having improved capacitance is provided. The element is formed from a pair of conductive sheets having a dielectric component laminated therebetween. The dielectric component is formed of two or more dielectric sheets, at least one of which can be partially cured followed by being fully cured. The lamination takes place by laminating a partially cured sheet to at least one other sheet of dielectric material and one of the conductive sheets. The total thickness of the two sheets of the dielectric component does not exceed about 4 rolls and preferably does not exceed about 3 mils; thus, the single dielectric sheet does not exceed about 2 mils and preferably does not exceed about 1.5 mils in thickness.

    摘要翻译： 提供一种形成用于具有改善的电容的电路板或芯片载体的电容元件的方法。 元件由一对导电片形成，其间具有介质成分。 电介质部件由两个或更多个电介质片材形成，其中至少一个电介质片材可部分固化，然后完全固化。 通过将部分固化的片材层压到至少一种其它电介质材料片和导电片材之一中来进行层压。 两片电介质组件的总厚度不超过约4卷，优选不超过约3密耳; 因此，单个电介质片材的厚度不超过约2密耳，优选不超过约1.5密耳。

    Printed circuit board capacitor structure and method
    7.
    发明授权
    Printed circuit board capacitor structure and method 失效
    印刷电路板电容器结构及方法

    公开(公告)号：US06574090B2

    公开(公告)日：2003-06-03

    申请号：US09822591

    申请日：2001-03-30

    申请人： Bernd K. Appelt ,  John M. Lauffer

    发明人： Bernd K. Appelt ,  John M. Lauffer

    IPC分类号： H01G420

    CPC分类号： H05K1/162 ,  H05K1/0366 ,  H05K3/429 ,  H05K3/4641 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/09309 ,  Y10T428/12569 ,  Y10T428/12597 ,  Y10T428/12903 ,  Y10T428/24124 ,  Y10T428/2476 ,  Y10T428/24994 ,  Y10T428/249952 ,  Y10T428/252 ,  Y10T428/264 ,  Y10T428/265 ,  Y10T428/269

    摘要： A capacitive element for a circuit board or chip carrier having improved capacitance and method of manufacturing the same is provided. The structure is formed from a pair of conductive sheets having a dielectric component laminated therebetween. The dielectric component is formed of two or more dielectric sheets, at least one of which can be partially cured or softened followed by being fully cured or hardened. The lamination takes place by laminating a partially cured or softened sheet to at least one other sheet of dielectric material and one of the sheets of conductive material. The total thickness of the two sheets of the dielectric component does not exceed about 4 mils and preferably does not exceed about 3 mils; thus, the single dielectric sheet does not exceed about 2 mils and preferably does not exceed about 1.5 mils in thickness. The use of two or more sheets of dielectric material makes it very unlikely that two or more defects in the sheets of dielectric material will align, thus greatly reducing the probability of a defect causing a failure in test or field use.

    摘要翻译： 提供了一种用于具有改进电容的电路板或芯片载体的电容元件及其制造方法。 该结构由一对导电片形成，其间具有介质成分。 电介质部件由两个或更多个电介质片形成，其中至少一个可部分固化或软化，然后完全固化或硬化。 通过将部分固化或软化的片材层压到至少一种其它电介质材料片和导电材料片之一中来进行层压。 两片电介质组件的总厚度不超过约4密耳，优选不超过约3密耳; 因此，单个电介质片材的厚度不超过约2密耳，优选不超过约1.5密耳。 使用两层或更多层电介质材料使电介质材料片中的两个或多个缺陷非常不可能对齐，从而大大降低了导致测试或现场使用失败的缺陷的可能性。

    Process for manufacturing a multi-layer circuit board
    9.
    发明授权
    Process for manufacturing a multi-layer circuit board 失效
    制造多层电路板的工艺

    公开(公告)号：US06391210B2

    公开(公告)日：2002-05-21

    申请号：US09901848

    申请日：2001-07-09

    申请人： Bernd K. Appelt ,  John M. Lauffer ,  Voya R. Markovich ,  Irving Memis ,  David J. Russell

    发明人： Bernd K. Appelt ,  John M. Lauffer ,  Voya R. Markovich ,  Irving Memis ,  David J. Russell

    IPC分类号： H01B1300

    CPC分类号： H05K3/4652 ,  H05K3/0023 ,  H05K3/0035 ,  H05K2203/0508 ,  H05K2203/0554

    摘要： A circuit board having a structure including a permanent photoimageable dielectric material suitable for fabrication of vias both by laser ablation, plasma ablation, or mechanical drilling techniques and by photoimaging techniques. A process is also disclosed for the manufacture of a multi-level circuit on a substrate having a first-level circuitry pattern on at least one side. The process comprises applying a permanent photoimageable dielectric over the first-level circuitry pattern; exposing the permanent photoimageable dielectric to radiation; laminating a conductive metal layer to the dielectric; making holes in the conductive metal layer and dielectric by mechanical drilling or by laser or plasma ablation; and making a second-level circuitry pattern and filling the holes with a conductive material to electrically connect the first and second layers of circuitry. A further process is claimed for designing a multi-level circuit board product comprising making a prototype having the above structure in which the holes are manufactured by mechanical drilling or by laser or plasma ablation, evaluating the prototype, and then manufacturing a commercial circuit board having essentially the same structure and materials of construction as the prototype, but wherein the holes are manufactured by photoimaging techniques.

    摘要翻译： 一种电路板，其结构包括适用于通过激光烧蚀，等离子体消融或机械钻孔技术制造通孔的永久可光成像介电材料，以及通过光成像技术。 还公开了一种用于在至少一侧具有第一级电路图案的衬底上制造多电平电路的工艺。 该过程包括在第一级电路图案上施加永久可光成像电介质; 将永久可光成像电介质暴露于辐射; 将导电金属层层叠到电介质上; 通过机械钻孔或通过激光或等离子体消融在导电金属层和电介质中形成孔; 以及制作二级电路图案，并用导电材料填充所述孔，以电连接所述第一和第二层电路。 要求设计多级电路板产品的另一方法包括制造具有上述结构的原型，其中通过机械钻孔或通过激光或等离子体烧蚀制造孔，评估原型，然后制造商业电路板，其具有 基本上与原型相同的结构和结构材料，但是其中孔通过光成像技术制造。

    Method for producing conductor interconnect with dendrites
    10.
    发明授权
    Method for producing conductor interconnect with dendrites 失效
    用枝晶生产导体互连的方法

    公开(公告)号：US06427323B2

    公开(公告)日：2002-08-06

    申请号：US09859690

    申请日：2001-05-17

    申请人： Bernd K. Appelt ,  Saswati Datta ,  Michael A. Gaynes ,  John M. Lauffer ,  James R. Wilcox

    发明人： Bernd K. Appelt ,  Saswati Datta ,  Michael A. Gaynes ,  John M. Lauffer ,  James R. Wilcox

    IPC分类号： H05K336

    CPC分类号： H05K3/325 ,  H05K3/4614 ,  H05K2201/0373 ,  H05K2201/09536 ,  H05K2201/10666 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49165 ,  Y10T29/49194

    摘要： A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.”

    摘要翻译： 提供了一种用于连接电子电路封装中的两个导电层的方法，包括以下步骤：在第一导电层的选定区域上形成枝晶，在第二导电层的选定区域上形成枝晶，在第一导电层上施加环氧粘合剂材料 并且将第二导电层压缩附接到第一导电层，使得第一导电层上的枝晶与第二导电层上的枝晶接触。 还要求保护的是包括用于根据本发明制造的电互连的树突的电子电路封装。 本发明的替代实施例利用具有树突的中间表面金属代替“通孔”。