公开(公告)号：US20090032975A1

公开(公告)日：2009-02-05

申请号：US12182283

申请日：2008-07-30

申请人： Byung Tai Do ,  Stephen A. Murphy ,  Yaojian Lin ,  Heap Hoe Kuan ,  Pandi Chelvam Marimuthu ,  Hin Hwa Goh

发明人： Byung Tai Do ,  Stephen A. Murphy ,  Yaojian Lin ,  Heap Hoe Kuan ,  Pandi Chelvam Marimuthu ,  Hin Hwa Goh

IPC分类号： H01L23/49 ,  H01L21/44

CPC分类号： H01L24/16 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/1411 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48711 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2224/85 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2224/48811 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012

摘要： A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer.

摘要翻译： 半导体晶片包含多个半导体管芯。 晶片具有在其表面上形成的接触垫。 在晶片上形成钝化层。 在钝化层上形成应力缓冲层。 将应力缓冲层图案化以暴露接触焊盘。 金属层沉积在应力缓冲层上。 金属层是用于与接触焊盘电接触的半导体器件的公共电压总线。 在与接触垫电接触的晶片之上形成粘合层，阻挡层和种子层。 金属层安装到种子层。 焊料凸块或其它互连结构形成在金属层上。 在金属层上形成第二钝化层。 在替代实施例中，可以将金属层沉积在金属层上，并且连接到金属层的引线键。

公开(公告)号：US08309451B2

公开(公告)日：2012-11-13

申请号：US12182283

申请日：2008-07-30

申请人： Byung Tai Do ,  Stephen A. Murphy ,  Yaojian Lin ,  Heap Hoe Kuan ,  Pandi Chelvam Marimuthu ,  Hin Hwa Goh

发明人： Byung Tai Do ,  Stephen A. Murphy ,  Yaojian Lin ,  Heap Hoe Kuan ,  Pandi Chelvam Marimuthu ,  Hin Hwa Goh

IPC分类号： H01L23/49 ,  H01L21/44

CPC分类号： H01L24/16 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/1411 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48711 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2224/85 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2224/48811 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012

摘要： A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer.

摘要翻译： 半导体晶片包含多个半导体管芯。 晶片具有在其表面上形成的接触垫。 在晶片上形成钝化层。 在钝化层上形成应力缓冲层。 将应力缓冲层图案化以暴露接触焊盘。 金属层沉积在应力缓冲层上。 金属层是用于与接触焊盘电接触的半导体器件的公共电压总线。 在与接触垫电接触的晶片之上形成粘合层，阻挡层和种子层。 金属层安装到种子层。 焊料凸块或其它互连结构形成在金属层上。 在金属层上形成第二钝化层。 在替代实施例中，可以将金属层沉积在金属层上，并且连接到金属层的引线键。

公开(公告)号：US20120261817A1

公开(公告)日：2012-10-18

申请号：US13536120

申请日：2012-06-28

申请人： Byung Tai Do ,  Stephen A. Murphy ,  Yaojian Lin ,  Heap Hoe Kuan ,  Pandi Chelvam Marimuthu ,  Hin Hwa Goh

发明人： Byung Tai Do ,  Stephen A. Murphy ,  Yaojian Lin ,  Heap Hoe Kuan ,  Pandi Chelvam Marimuthu ,  Hin Hwa Goh

IPC分类号： H01L21/768 ,  H01L23/498

CPC分类号： H01L24/16 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/1411 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48711 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2224/85 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2224/48811 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012

摘要： A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer.

摘要翻译： 半导体晶片包含多个半导体管芯。 晶片具有在其表面上形成的接触垫。 在晶片上形成钝化层。 在钝化层上形成应力缓冲层。 将应力缓冲层图案化以暴露接触焊盘。 金属层沉积在应力缓冲层上。 金属层是用于与接触焊盘电接触的半导体器件的公共电压总线。 在与接触垫电接触的晶片之上形成粘合层，阻挡层和种子层。 金属层安装到种子层。 焊料凸块或其它互连结构形成在金属层上。 在金属层上形成第二钝化层。 在替代实施例中，可以将金属层沉积在金属层上，并且连接到金属层的引线键。

公开(公告)号：US08624364B2

公开(公告)日：2014-01-07

申请号：US12714431

申请日：2010-02-26

申请人： Seng Guan Chow ,  Hin Hwa Goh ,  Rui Huang ,  Heap Hoe Kuan

发明人： Seng Guan Chow ,  Hin Hwa Goh ,  Rui Huang ,  Heap Hoe Kuan

IPC分类号： H01L23/495

CPC分类号： H01L25/105 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit packaging system includes: a base integrated circuit package having a base integrated circuit on a base substrate thereof; a base barrier on the base substrate adjacent a base perimeter of the base substrate; a stack substrate over the base substrate, the stack substrate having a stack substrate aperture with the stack substrate having an inter-substrate connector thereon; a connector underfill through the stack substrate aperture encapsulating the inter-substrate connector, overflow of the connector underfill prevented by the base barrier; and a cavity formed of the stack substrate, the base integrated circuit package, and the connector underfill, the cavity horizontally offset from the base barrier.

摘要翻译： 一种集成电路封装系统，包括：基底集成电路封装，在其基底上具有基底集成电路; 在所述基底基板上邻近所述基底基底的周边的基底屏障; 所述堆叠衬底具有堆叠衬底孔，所述堆叠衬底在其上具有衬底间连接器; 通过封装衬底间连接器的堆叠衬底孔径的底部填充剂的底部填充物，由基底屏障阻止的连接器底部填充物溢出; 以及由堆叠衬底，基底集成电路封装和连接器底部填充物形成的空腔，空腔与基底屏障水平偏移。

公开(公告)号：US20120061854A1

公开(公告)日：2012-03-15

申请号：US12881983

申请日：2010-09-14

申请人： Seng Guan Chow ,  Hin Hwa Goh ,  Rui Huang ,  Heap Hoe Kuan

发明人： Seng Guan Chow ,  Hin Hwa Goh ,  Rui Huang ,  Heap Hoe Kuan

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H01L21/563 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a bottom substrate; mounting a bottom integrated circuit over the bottom substrate; mounting a top substrate over a side of the bottom integrated circuit opposite the bottom substrate; connecting a top interconnect between the bottom substrate and the top substrate; and forming an underfill layer between the bottom substrate and the top substrate, the underfill layer encapsulating the top interconnect outside a perimeter of the bottom integrated circuit.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供底部基板; 将底部集成电路安装在底部基板上; 在底部集成电路的与底部基板相对的一侧上安装顶部基板; 连接底部基板和顶部基板之间的顶部互连; 并且在底部基板和顶部基板之间形成底部填充层，底部填充层将顶部互连件封装在底部集成电路的周边外部。

公开(公告)号：US08304880B2

公开(公告)日：2012-11-06

申请号：US12881983

申请日：2010-09-14

申请人： Seng Guan Chow ,  Hin Hwa Goh ,  Rui Huang ,  Heap Hoe Kuan

发明人： Seng Guan Chow ,  Hin Hwa Goh ,  Rui Huang ,  Heap Hoe Kuan

IPC分类号： H01L23/02

CPC分类号： H01L21/563 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a bottom substrate; mounting a bottom integrated circuit over the bottom substrate; mounting a top substrate over a side of the bottom integrated circuit opposite the bottom substrate; connecting a top interconnect between the bottom substrate and the top substrate; and forming an underfill layer between the bottom substrate and the top substrate, the underfill layer encapsulating the top interconnect outside a perimeter of the bottom integrated circuit.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供底部基板; 将底部集成电路安装在底部基板上; 在底部集成电路的与底部基板相对的一侧上安装顶部基板; 连接底部基板和顶部基板之间的顶部互连; 并且在底部基板和顶部基板之间形成底部填充层，底部填充层将顶部互连件封装在底部集成电路的周边外部。

公开(公告)号：US20110210436A1

公开(公告)日：2011-09-01

申请号：US12714431

申请日：2010-02-26

申请人： Seng Guan Chow ,  Hin Hwa Goh ,  Rui Huang ,  Heap Hoe Kuan

发明人： Seng Guan Chow ,  Hin Hwa Goh ,  Rui Huang ,  Heap Hoe Kuan

IPC分类号： H01L25/065 ,  H01L21/60

CPC分类号： H01L25/105 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base integrated circuit on the base substrate; attaching a base barrier on the base substrate adjacent a base perimeter thereof; mounting a stack substrate over the base substrate, the stack substrate having a stack substrate aperture with the stack substrate having an inter-substrate connector thereon; and dispensing a connector underfill through the stack substrate aperture encapsulating the inter-substrate connector, overflow of the connector underfill prevented by the base barrier.

摘要翻译： 一种制造集成电路封装系统的方法，包括：提供基底; 将基底集成电路附接在基底基板上; 在基底基板上邻近其基部周边附接基底屏障; 将堆叠衬底安装在基底衬底上，所述堆叠衬底具有堆叠衬底孔，所述堆叠衬底在其上具有衬底间连接器; 并且通过封装衬底间连接器的堆叠衬底孔分配连接器底部填充物，由基底屏障防止的连接器底部填充物溢出。

公开(公告)号：US08456002B2

公开(公告)日：2013-06-04

申请号：US13333739

申请日：2011-12-21

申请人： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Hin Hwa Goh ,  Yu Gu ,  Il Kwon Shim ,  Rui Huang ,  Seng Guan Chow ,  Jianmin Fang ,  Xia Feng

发明人： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Hin Hwa Goh ,  Yu Gu ,  Il Kwon Shim ,  Rui Huang ,  Seng Guan Chow ,  Jianmin Fang ,  Xia Feng

IPC分类号： H01L23/52

CPC分类号： H01L23/3114 ,  H01L21/31 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/528 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2224/214

摘要： A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

公开(公告)号：US20130113092A9

公开(公告)日：2013-05-09

申请号：US13333739

申请日：2011-12-21

申请人： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Hin Hwa Goh ,  Yu Gu ,  Il Kwon Shim ,  Rui Huang ,  Seng Guan Chow ,  Jianmin Fang ,  Xia Feng

发明人： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Hin Hwa Goh ,  Yu Gu ,  Il Kwon Shim ,  Rui Huang ,  Seng Guan Chow ,  Jianmin Fang ,  Xia Feng

IPC分类号： H01L23/52 ,  H01L21/56 ,  H01L21/78

CPC分类号： H01L23/3114 ,  H01L21/31 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/528 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2224/214

摘要： A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

摘要翻译： 半导体器件具有形成在半导体管芯的表面上的半导体管芯和导电层。 可以在半导体管芯中形成第一通道。 密封剂沉积在半导体管芯上。 可以在密封剂中形成第二通道。 在半导体管芯和第一导电层上形成第一绝缘层并进入第一沟道。 第一绝缘层延伸到第二通道中。 第一绝缘层的拉伸强度大于150MPa，伸长率在35-150％之间，厚度为2-30微米。 在形成第一绝缘层之前，可以在半导体管芯上方形成第二绝缘层。 在半导体管芯和密封剂上形成互连结构。 互连结构电连接到第一导电层。 第一绝缘层在形成互连结构期间提供应力释放。

公开(公告)号：US08648470B2

公开(公告)日：2014-02-11

申请号：US13326157

申请日：2011-12-14

申请人： Yaojian Lin ,  Jose Alvin Caparas ,  Kang Chen ,  Hin Hwa Goh

发明人： Yaojian Lin ,  Jose Alvin Caparas ,  Kang Chen ,  Hin Hwa Goh

IPC分类号： H01L23/538

CPC分类号： H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/00 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73259 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81

摘要： A semiconductor device has a first semiconductor die including TSVs mounted to a carrier with a thermally releasable layer. A first encapsulant having a first coefficient of thermal expansion CTE is deposited over the first semiconductor die. The first encapsulant includes an elevated portion in a periphery of the first encapsulant that reduces warpage. A surface of the TSVs is exposed. A second semiconductor die is mounted to the surface of the TSVs and forms a gap between the first and second semiconductor die. A second encapsulant having a second CTE is deposited over the first and second semiconductor die and within the gap. The first CTE is greater than the second CTE. In one embodiment, the first and second encapsulants are formed in a chase mold. An interconnect structure is formed over the first and second semiconductor die.

摘要翻译： 半导体器件具有第一半导体管芯，其包括安装在具有热可释放层的载体上的TSV。 具有第一热膨胀系数CTE的第一密封剂沉积在第一半导体管芯上。 第一密封剂包括第一密封剂的周边中的升高部分，其减少翘曲。 暴露TSV的表面。 第二半导体管芯安装到TSV的表面，并在第一和第二半导体管芯之间形成间隙。 具有第二CTE的第二密封剂沉积在第一和第二半导体管芯上并且在间隙内。 第一个CTE大于第二个CTE。 在一个实施例中，第一和第二密封剂形成在追逐模具中。 在第一和第二半导体管芯上形成互连结构。