摘要:
A clad solder thermal interface material is described. In one example the material has a a first layer of solder having a melting temperature lower than a temperature of a particular solder reflow furnace, a second layer of solder clad to the first layer of solder, the second layer having a melting temperature higher than the temperature of the solder reflow furnace, and a third layer of solder clad to the second layer of solder opposite the first layer, the third layer having a melting temperature lower than the temperature of the solder reflow furnace.
摘要:
A clad solder thermal interface material is described. In one example the material has a a first layer of solder having a melting temperature lower than a temperature of a particular solder reflow furnace, a second layer of solder clad to the first layer of solder, the second layer having a melting temperature higher than the temperature of the solder reflow furnace, and a third layer of solder clad to the second layer of solder opposite the first layer, the third layer having a melting temperature lower than the temperature of the solder reflow furnace.
摘要:
This disclosure relates generally to an electronic package and methods that include an electrically conductive pad, a package insulator layer including a substantially non-conductive material, the package insulator layer being substantially planar, and a via. The via may be formed within the package insulator layer and electrically coupled to the electrically conductive pad. The via may include a conductor extending vertically through at least part of the package insulator layer and having a first end proximate the electrically conductive pad and a second end opposite the first end and a finish layer secured to the second end of the conductor, the finish layer including a gold compound.
摘要:
The present disclosure relates to the field of fabricating microelectronic packages, wherein magnetic particles distributed within a solder paste may be used to form a magnetic intermetallic compound interconnect. The intermetallic compound interconnect may be exposed to a magnetic field, which can heat a solder material to a reflow temperature for attachment of microelectronic components comprising the microelectronic packages.
摘要:
A coating for a microelectronic device comprises a polymer film (131) containing a filler material (232). The polymer film has a thermal conductivity greater than 3 W/m·K and a thickness (133) that does not exceed 10 micrometers. The polymer film may be combined with a dicing tape (310) to form a treatment (300) that simplifies a manufacturing process for a microelectronic package (100) and may be used in order to manage a thermal profile of the microelectronic device.
摘要:
The present disclosure relates to the field of fabricating microelectronic packages, wherein microelectronic components of the microelectronic packages may have sintered conductive vias comprising sintered metal and magnetic particles.
摘要:
Methods and associated structures of forming underfill material are described. Those methods may include applying an underfill to an interconnect structure comprising residue from a no clean flux, wherein the underfill comprises at least one of a functionalized nanofiller and a micron-sized filler.
摘要:
A semiconductor package is described. The semiconductor package includes a substrate and an integrated heat spreader disposed above and coupled with the substrate. A cavity is disposed between the substrate and the integrated heat spreader. A semiconductor die is disposed above the substrate and in the cavity. An array of first-level solder joints is disposed between the substrate and the semiconductor die. A layer of magnetic particle-based composite material is also disposed in the cavity.
摘要:
Embodiments of the present disclosure are directed to an interconnect cable including a edge finger connector, and associated configurations and methods. The edge finger connector may be disposed at a first end of the interconnect cable and may connect the interconnect cable to an edge finger included in or coupled to a package substrate. The package substrate may be included in a processor package assembly, and a processor may be mounted on the substrate. The interconnect cable may include one or more elongate conductors, with contacts directly coupled to respective conductors. A second connector may be disposed at a second end of the interconnect cable, and may couple the interconnect cable to a small form-factor pluggable (SFP) case that is configured to connect the interconnect cable to an SFP cable. Other embodiments may be described and claimed.
摘要:
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure.