公开(公告)号：US06900142B2

公开(公告)日：2005-05-31

申请号：US10604560

申请日：2003-07-30

申请人： Emanual I. Cooper ,  John M. Cotte ,  Lisa A. Fanti ,  David E. Eichstadt ,  Stephen J. Kilpatrick ,  Henry A. Nye, III ,  Donna S. Zupanski-Nielsen

发明人： Emanual I. Cooper ,  John M. Cotte ,  Lisa A. Fanti ,  David E. Eichstadt ,  Stephen J. Kilpatrick ,  Henry A. Nye, III ,  Donna S. Zupanski-Nielsen

IPC分类号： H01L21/302 ,  H01L21/44 ,  H01L21/461 ,  H01L21/60

CPC分类号： H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/00014

摘要： A method is provided for removing exposed seed layers in the fabrication of solder interconnects on electronic components such as semiconductor wafers without damaging the interconnects or underlying wafer substrate and with a high wafer yield. The solder interconnects are lead free or substantially lead free and typically contain Sn. An oxalic acid solution is used to contact the wafer after an etching step to remove part of the seed layer. The seed layer is typically a Cu containing layer with a lower barrier layer containing barrier metals such as Ti, Ta and W. The lower barrier layer remains after the etch and the oxalic acid solution inhibits the formation of Sn compounds on the barrier layer surface which compounds may mask the barrier layer and the barrier layer etchant resulting in incomplete barrier layer removal on the wafer surface. Any residual conductive barrier layer can cause shorts and other wafer problems and result in a lower wafer yield. An electroetch is preferred to remove the portion of the seed layer overlying the lower barrier layer.

摘要翻译： 提供了一种在电子部件如半导体晶片制造焊料互连件中去除暴露的种子层的方法，而不会损坏互连或下面的晶片衬底并以高的晶片产量。 焊料互连是无铅的或基本上无铅的，并且通常含有Sn。 在蚀刻步骤之后，使用草酸溶液接触晶片以除去部分种子层。 种子层通常是含Cu层，其具有包含阻挡金属如Ti，Ta和W的下阻挡层。在蚀刻后保留下阻挡层，并且草酸溶液抑制在阻挡层表面上形成Sn化合物 化合物可以掩蔽阻挡层和阻挡层蚀刻剂，导致晶片表面上不完全的阻挡层去除。 任何残留的导电阻挡层可能导致短路和其他晶片问题，并导致较低的晶圆产量。 优选去除电子蚀刻以去除覆盖在下阻挡层上的种子层的部分。

公开(公告)号：US20120325316A1

公开(公告)日：2012-12-27

申请号：US13604230

申请日：2012-09-05

申请人： John M. Cotte ,  Laura L. Kosbar ,  Deborah A. Neumayer ,  Xiaoyan Shao

发明人： John M. Cotte ,  Laura L. Kosbar ,  Deborah A. Neumayer ,  Xiaoyan Shao

IPC分类号： H01L31/0232

CPC分类号： H01L31/02168 ,  H01L31/022425 ,  H01L31/068 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A method to determine the cleanness of a semiconductor substrate and the quantity/density of pin holes that may exist within a patterned antireflective coating (ARC) is provided. Electroplating is employed to monitor the changes in the porosity of the ARC caused by the pin holes during solar cell manufacturing. In particular, electroplating a metal or metal alloy to form a metallic grid on an exposed front side surface of a substrate also fills the pin holes. The quantity/density of metallic filled pin holes (and hence the number of pin holes) in the patterned ARC can then be determined.

摘要翻译： 提供了确定半导体衬底的清洁度的方法以及可能存在于图案化抗反射涂层（ARC）内的针孔的数量/密度。 使用电镀来监测由太阳能电池制造过程中的针孔引起的ARC孔隙度的变化。 特别地，在基板的暴露的前侧表面上电镀金属或金属合金以形成金属网格也填充针孔。 然后可以确定图案化的ARC中的金属填充针孔的数量/密度（以及因此的孔的数量）。

公开(公告)号：US20120322243A1

公开(公告)日：2012-12-20

申请号：US13596593

申请日：2012-08-28

申请人： Veeraraghavan S. Basker ,  John M. Cotte ,  Hariklia Deligianni ,  Matteo Flotta

发明人： Veeraraghavan S. Basker ,  John M. Cotte ,  Hariklia Deligianni ,  Matteo Flotta

IPC分类号： H01L21/326

CPC分类号： C25D5/54 ,  C25D5/006 ,  C25D5/02 ,  C25D7/123 ,  C25D11/005 ,  C25D11/024 ,  C25D17/001 ,  C25F3/14 ,  H01L21/28079 ,  H01L21/2885

摘要： An electrochemical process comprising: providing a 125 mm or larger semiconductor wafer in electrical contact with a conducting surface, wherein at least a portion of the semiconductor wafer is in contact with an electrolytic solution, said semiconductor wafer functioning as a first electrode; providing a second electrode in the electrolytic solution, the first and second electrode connected to opposite ends of an electric power source; and irradiating a surface of the semiconductor wafer with a light source as an electric current is applied across the first and the second electrodes. The invention is also directed to an apparatus including a light source and electrochemical components to conduct the electrochemical process.

公开(公告)号：US08263497B2

公开(公告)日：2012-09-11

申请号：US12352718

申请日：2009-01-13

申请人： Paul S. Andry ,  John M. Cotte ,  Michael F. Lofaro ,  Edmund J. Sprogis ,  James A. Tornello ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  John M. Cotte ,  Michael F. Lofaro ,  Edmund J. Sprogis ,  James A. Tornello ,  Cornelia K. Tsang

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： An assembly including a main wafer having a body with a front side and a back side and a plurality of blind electrical vias terminating above the back side, and a handler wafer, is obtained. A step includes exposing the blind electrical vias to various heights on the back side. Another step involves applying a first chemical mechanical polish process to the back side, to open any of the surrounding insulator adjacent the end regions of the cores remaining after the exposing step, and to co-planarize the via conductive cores, the surrounding insulator adjacent the side regions of the cores, and the body of the main wafer. Further steps include etching the back side to produce a uniform standoff height of each of the vias across the back side; depositing a dielectric across the back side; and applying a second chemical mechanical polish process to the back side.

摘要翻译： 获得包括具有前侧和后侧的主体的主晶片和终止于背面的多个盲电通路的组件和处理器晶片。 一个步骤包括将盲电通孔暴露在背面的各种高度上。 另一个步骤涉及将第一化学机械抛光工艺应用于背面，以便打开暴露步骤之后残留的芯的端部附近的任何周围的绝缘体，并且将通孔导电芯，邻近的绝缘体 芯的侧面区域和主晶片的主体。 进一步的步骤包括蚀刻背面以产生穿过背面的每个通路的均匀间隔高度; 在背面沉积电介质; 并向后侧施加第二化学机械抛光工艺。

公开(公告)号：US07843067B2

公开(公告)日：2010-11-30

申请号：US12053969

申请日：2008-03-24

申请人： John M. Cotte ,  Balasubramanian Haran ,  Christopher C. Parks ,  Xiaoyan Shao ,  Eva E. Simonyi

发明人： John M. Cotte ,  Balasubramanian Haran ,  Christopher C. Parks ,  Xiaoyan Shao ,  Eva E. Simonyi

IPC分类号： H01L23/48

CPC分类号： H01L21/76843 ,  H01L21/2885 ,  H01L21/76873 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T428/26 ,  H01L2924/00

摘要： The present disclosure relates to a microelectronic structure and the manufacture of the microelectronic structure. Specifically, the disclosure relates to an interconnect barrier layer between a rhodium contact structure and a copper interconnect structure in a microelectronic structure. The microelectronic structure provides for low resistance in microelectronic devices.

摘要翻译： 本公开涉及微电子结构和微电子结构的制造。 具体地，本公开涉及在微电子结构中的铑接触结构和铜互连结构之间的互连势垒层。 微电子结构在微电子器件中提供低电阻。

公开(公告)号：US07829427B2

公开(公告)日：2010-11-09

申请号：US12612743

申请日：2009-11-05

申请人： Daniel C. Edelstein ,  Panayotis C. Andricacos ,  John M. Cotte ,  Hariklia Deligianni ,  John H. Magerlein ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Richard P. Volant

发明人： Daniel C. Edelstein ,  Panayotis C. Andricacos ,  John M. Cotte ,  Hariklia Deligianni ,  John H. Magerlein ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Richard P. Volant

IPC分类号： H01L21/20

CPC分类号： H01L24/12 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method of forming an inductor. The method including: (a) forming a dielectric layer on a top surface of a substrate; after (a), (b) forming a lower trench in the dielectric layer; after (b), (c) forming a resist layer on a top surface of the dielectric layer; after (c), (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and after (d), (e) completely filling the lower trench and at least partially filling the upper trench with a conductor in order to form the inductor.

摘要翻译： 一种形成电感器的方法。 该方法包括：（a）在基板的顶表面上形成电介质层; （a）之后，（b）在介电层中形成下沟槽; （b）之后，（c）在介电层的顶表面上形成抗蚀剂层; 在（c）之后，（d）在抗蚀剂层中形成上沟槽，上沟槽与下沟槽对准，上沟槽的底部通向下沟槽; 在（d）之后，（e）完全填充下沟槽并且用导体至少部分地填充上沟槽以形成电感器。

公开(公告)号：US20090057154A1

公开(公告)日：2009-03-05

申请号：US12198274

申请日：2008-08-26

申请人： Veeraraghavan S. Basker ,  John M. Cotte ,  Hariklia Deligianni ,  Matteo Flotta

发明人： Veeraraghavan S. Basker ,  John M. Cotte ,  Hariklia Deligianni ,  Matteo Flotta

IPC分类号： C25D7/12 ,  C25D5/00 ,  C25D17/10

CPC分类号： C25D5/54 ,  C25D5/006 ,  C25D5/02 ,  C25D7/123 ,  C25D11/005 ,  C25D11/024 ,  C25D17/001 ,  C25F3/14 ,  H01L21/28079 ,  H01L21/2885

摘要： An electrochemical process comprising: providing a 125 mm or larger semiconductor wafer in electrical contact with a conducting surface, wherein at least a portion of the semiconductor wafer is in contact with an electrolytic solution, said semiconductor wafer functioning as a first electrode; providing a second electrode in the electrolytic solution, the first and second electrode connected to opposite ends of an electric power source; and irradiating a surface of the semiconductor wafer with a light source as an electric current is applied across the first and the second electrodes. The invention is also directed to an apparatus including a light source and electrochemical components to conduct the electrochemical process.

摘要翻译： 一种电化学方法，包括：提供与导电表面电接触的125mm或更大的半导体晶片，其中所述半导体晶片的至少一部分与电解液接触，所述半导体晶片用作第一电极; 在所述电解液中提供第二电极，所述第一和第二电极连接到电源的相对端; 并且在第一和第二电极之间施加用作为电流的光源照射半导体晶片的表面。 本发明还涉及一种包括光源和用于进行电化学过程的电化学组分的设备。

公开(公告)号：US07485964B2

公开(公告)日：2009-02-03

申请号：US11399579

申请日：2006-04-06

申请人： John M. Cotte ,  Kenneth John McCullough ,  Wayne Martin Moreau ,  Kevin Petrarca ,  John P. Simons ,  Charles J. Taft ,  Richard Volant

发明人： John M. Cotte ,  Kenneth John McCullough ,  Wayne Martin Moreau ,  Kevin Petrarca ,  John P. Simons ,  Charles J. Taft ,  Richard Volant

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/02118 ,  H01L21/0212 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/31058 ,  H01L21/312 ,  H01L21/3121 ,  H01L21/31695 ,  H01L21/7682 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T428/249978 ,  Y10T428/24999 ,  H01L2924/00

摘要： A dielectric material formed by contacting a low dielectric constant polymer with liquid or supercritical carbon dioxide, under thermodynamic conditions which maintain the carbon dioxide in the liquid or supercritical state, wherein a porous product is formed. Thereupon, thermodynamic conditions are changed to ambient wherein carbon dioxide escapes from the pores and is replaced with air.

摘要翻译： 在将二氧化碳保持在液态或超临界状态的热力学条件下，通过使低介电常数聚合物与液体或超临界二氧化碳接触而形成的电介质材料，其中形成多孔产品。 因此，热力学条件改变为环境，其中二氧化碳从孔中逸出并被空气替代。

公开(公告)号：US07288155B2

公开(公告)日：2007-10-30

申请号：US11128022

申请日：2005-05-12

申请人： John P. Simons ,  Kenneth J. McCullough ,  Wayne M. Moreau ,  John M. Cotte ,  Keith R. Pope ,  Charles J. Taft ,  Dario Goldfarb

发明人： John P. Simons ,  Kenneth J. McCullough ,  Wayne M. Moreau ,  John M. Cotte ,  Keith R. Pope ,  Charles J. Taft ,  Dario Goldfarb

IPC分类号： B08B3/00 ,  B08B7/04

CPC分类号： H01L21/02101 ,  B08B7/0021 ,  H01L21/67109 ,  H01L21/67248 ,  Y10S134/902

摘要： A method for cleaning a semiconductor structure including providing a chamber for holding the semiconductor structure and a dense phase fluid, providing a thermal transfer device having a thermal transfer surface, connecting the thermal transfer device to the chamber, placing the semiconductor structure in the chamber in contact with the thermal transfer surface and thermally cycling the thermal transfer surface.

摘要翻译： 一种用于清洁半导体结构的方法，包括提供用于保持半导体结构的腔室和致密相流体，提供具有热转印表面的热转印装置，将热转印装置连接到腔室，将半导体结构放置在腔室中 与热转印表面接触并热循环热转印表面。

公开(公告)号：US07068138B2

公开(公告)日：2006-06-27

申请号：US10768773

申请日：2004-01-29

申请人： Daniel C. Edelstein ,  Panayotis C. Andricacos ,  John M. Cotte ,  Hariklia Deligianni ,  John H. Magerlein ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Richard P. Volant

发明人： Daniel C. Edelstein ,  Panayotis C. Andricacos ,  John M. Cotte ,  Hariklia Deligianni ,  John H. Magerlein ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Richard P. Volant

IPC分类号： H01F27/24

CPC分类号： H01L24/12 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： An inductor and a method of forming and the inductor, the method including: (a) providing a semiconductor substrate; (b) forming a dielectric layer on a top surface of the substrate; (c) forming a lower trench in the dielectric layer; (d) forming a resist layer on a top surface of the dielectric layer; (e) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and (f) completely filling the lower trench at least partially filling the upper trench with a conductor in order to form the inductor. The inductor including a top surface, a bottom surface and sidewalls, a lower portion of said inductor extending a fixed distance into a dielectric layer formed on a semiconductor substrate and an upper portion extending above said dielectric layer; and means to electrically contact said inductor.

摘要翻译： 一种电感器及其形成方法和电感器，所述方法包括：（a）提供半导体衬底; （b）在所述基板的顶表面上形成电介质层; （c）在介电层中形成下沟槽; （d）在介电层的顶表面上形成抗蚀剂层; （e）在所述抗蚀剂层中形成上沟槽，所述上沟槽对准所述下沟槽，所述上沟槽的底部通向所述下沟槽; 和（f）用导体完全填充下沟槽至少部分地填充上沟槽，以形成电感器。 所述电感器包括顶表面，底表面和侧壁，所述电感器的下部将固定距离延伸到形成在半导体衬底上的电介质层和在所述电介质层上方延伸的上部; 以及用于电接触所述电感器的装置。