公开(公告)号：US08664778B2

公开(公告)日：2014-03-04

申请号：US13531842

申请日：2012-06-25

Applicant: Francois Marion

Inventor： Francois Marion

IPC: H01L23/28

CPC classification number: H01L21/563 ,  B81C1/00293 ,  B81C2203/0118 ,  B81C2203/0145 ,  H01L21/56 ,  H01L23/043 ,  H01L23/053 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/3128 ,  H01L2224/73203 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A method for manufacturing a microelectronic assembly including stacked first and second microelectronic components having a cavity therebetween including defining said cavity by means of a lateral wall forming a closed frame extending around a determined area of the first component except for an opening used as a vent; forming within the closed frame and opposite to the vent an obstacle capable of forming, in cooperation with the lateral wall, a bypass duct for the filling material; performing a flip-chip hybridization of the first and second components, a surface of the second component resting on the upper edge or end of the lateral wall formed on the first component to form said at least one cavity; injecting the filling material in liquid form between the two hybridized components to embed said at least one cavity and to make it tight by obstruction of the vent as said filling material solidifies.

Abstract translation: 一种用于制造微电子组件的方法，包括堆叠的第一和第二微电子部件，其间具有空腔，包括通过侧壁限定所述空腔，侧壁形成围绕第一部件的确定区域延伸的封闭框架，除了用作通风口的开口; 在闭合框架内并与通风口相对形成能够与侧壁协作形成用于填充材料的旁路管道的障碍物; 执行第一和第二部件的倒装芯片杂交，第二部件的表面搁置在形成在第一部件上的侧壁的上边缘或端部上以形成所述至少一个腔; 在两个杂化组分之间注入液体形式的填充材料以嵌入所述至少一个空腔，并且当所述填充材料固化时通过堵塞通气孔使其紧密。

公开(公告)号：US08093728B2

公开(公告)日：2012-01-10

申请号：US12558149

申请日：2009-09-11

Applicant: Francois Marion

Inventor： Francois Marion

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05558 ,  H01L2224/05571 ,  H01L2224/1147 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16503 ,  H01L2224/81136 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/85365 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/0106 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/1461 ,  H01L2924/19105 ,  H01L2924/351 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4092 ,  H05K2201/0367 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A connection device between two components includes a hollow conductive insert, into which is fitted another conductive insert, the electrical connection between the two inserts being provided by means of a solder element.

Abstract translation: 两个部件之间的连接装置包括中空导电插入件，其中安装有另一个导电插入件，两个插入件之间的电连接通过焊接元件提供。

公开(公告)号：US07938311B2

公开(公告)日：2011-05-10

申请号：US11495214

申请日：2006-07-28

Applicant: Francois Marion

Inventor： Francois Marion

IPC: B23K31/02

CPC classification number: H05K3/3436 ,  H01L23/49811 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/81143 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/381 ,  H05K2201/094 ,  H05K2201/097 ,  H05K2203/0465 ,  H05K2203/048 ,  Y02P70/613 ,  H01L2924/00014

Abstract: The hybridization method provides a first component with first pads and a second component with second pads for accommodating protrusions of a fusible material, so that the first pads and second pads line up two by two in order to form pairs of pads to interconnect the two components when aligned. Then placing the first and second components one on top of the other to form an assembly where some of the protrusions of fusible material on the first and/or second pads respectively consist of at least three larger-sized protrusions, especially taller protrusions, so that before the temperature is increased to the hybridization temperature of the fusible material, the component only rests on the larger protrusions.

Abstract translation: 杂交方法提供了具有第一焊盘的第一部件和具有用于容纳可熔材料的突起的第二焊盘的第二部件，使得第一焊盘和第二焊盘两排二排，以便形成一对焊盘以互连两个部件 对齐时。 然后将第一和第二部件放置在另一个之上，以形成组件，其中第一和/或第二垫上的可熔材料的一些突起分别由至少三个较大尺寸的突起，特别是较高的突起组成，使得 在温度升高到易熔材料的杂交温度之前，该部件仅在更大的突起上。

公开(公告)号：US07645686B2

公开(公告)日：2010-01-12

申请号：US12212302

申请日：2008-09-17

Applicant: Manuel Fendler ,  Abdenacer Ait-Mani ,  Alain Gueugnot ,  Francois Marion

Inventor： Manuel Fendler ,  Abdenacer Ait-Mani ,  Alain Gueugnot ,  Francois Marion

IPC: H01L21/00

CPC classification number: H01L21/6835 ,  H01L21/78 ,  H01L24/83 ,  H01L24/97 ,  H01L27/1469 ,  H01L2221/68354 ,  H01L2221/68377 ,  H01L2224/32014 ,  H01L2224/83191 ,  H01L2224/95001 ,  H01L2224/95136 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01052 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/16195 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2924/00

Abstract: The invention concerns a method of collective bonding of individual chips on a strained substrate (44), which comprises the following steps: functionalised layers (40) are arranged on a support (41), in an adjacent non-contiguous manner, with a space e between two neighboring layers (40), a calibrated drop of adhesive (43) is deposited on each of these functionalised layers, the strained substrate (44) is transferred onto these drops of adhesive, the parts of the assembly thereby formed are singularized to produce chips (45) bonded to the surface of strained substrate. The invention also concerns a method of placing under strain a semiconductor reading circuit by a substrate in a material of different coefficient of expansion.

Abstract translation: 本发明涉及一种在应变衬底（44）上单独芯片的集体结合的方法，该方法包括以下步骤：功能化层（40）以相邻的非连续方式与支撑体（41）以空间 在两个相邻层（40）之间，在每个这些功能化层上沉积校准的粘合剂层（43），将应变基底（44）转移到这些粘合剂层上，由此形成的组件的部分被单数化为 产生结合到应变表面的芯片（45）。 本发明还涉及一种通过衬底在不同膨胀系数的材料中使半导体读取电路处于应变状态的方法。

公开(公告)号：US20090085045A1

公开(公告)日：2009-04-02

申请号：US12330805

申请日：2008-12-09

Applicant: Francois Marion ,  Olivier Gravrand

Inventor： Francois Marion ,  Olivier Gravrand

IPC: H01L21/82 ,  H01L25/065 ,  H01L25/04 ,  H01L25/075 ,  H01S5/00

CPC classification number: H01L24/95 ,  H01L21/6835 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0753 ,  H01L25/50 ,  H01L33/62 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01052 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01093 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The invention relates to a method for producing a matrix of electronic components, comprising a step of producing an active layer on a substrate, and a step of individualizing the components by forming trenches in the active layer at least until the substrate emerges. The method comprises steps of depositing a layer of functional material on the active layer, depositing a photosensitive resin on the layer of material in such a way as to fill said trenches and to form a thin film on the upper face of the components, at least partially exposing the resin to radiation while underexposing the portion of resin in the trenches, developing the resin in such a way as to remove the properly exposed portion thereof, removing the functional material layer portion that shows through after the development step, and removing the remaining portion of resin.

Abstract translation: 本发明涉及一种用于制造电子元件基质的方法，包括在基底上制备活性层的步骤，以及通过在活性层中形成沟槽至少直至基底露出来使组分个体化的步骤。 该方法包括以下步骤：在有源层上沉积一层功能材料，将光敏树脂沉积在材料层上，以便填充所述沟槽并在组件的上表面上形成薄膜，至少 将树脂部分地暴露于辐射，同时使沟槽中树脂的部分露出，同时将树脂显影以除去适当暴露的部分，除去显影步骤后通过的功能材料层部分，并除去剩余的 部分树脂。

公开(公告)号：US20090075423A1

公开(公告)日：2009-03-19

申请号：US12212302

申请日：2008-09-17

Applicant: Manuel Fendler ,  Abdenacer Ait-Mani ,  Alain Gueugnot ,  Francois Marion

Inventor： Manuel Fendler ,  Abdenacer Ait-Mani ,  Alain Gueugnot ,  Francois Marion

IPC: H01L21/00

CPC classification number: H01L21/6835 ,  H01L21/78 ,  H01L24/83 ,  H01L24/97 ,  H01L27/1469 ,  H01L2221/68354 ,  H01L2221/68377 ,  H01L2224/32014 ,  H01L2224/83191 ,  H01L2224/95001 ,  H01L2224/95136 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01052 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/16195 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2924/00

Abstract: The invention concerns a method of collective bonding of individual chips on a strained substrate (44), which comprises the following steps: functionalised layers (40) are arranged on a support (41), in an adjacent non-contiguous manner, with a space e between two neighbouring layers (40), a calibrated drop of adhesive (43) is deposited on each of these functionalised layers, the strained substrate (44) is transferred onto these drops of adhesive, the parts of the assembly thereby formed are singularised to produce chips (45) bonded to the surface of strained substrate. The invention also concerns a method of placing under strain a semiconductor reading circuit by a substrate in a material of different coefficient of expansion.

Abstract translation: 本发明涉及一种在应变衬底（44）上单独芯片的集体结合的方法，该方法包括以下步骤：功能化层（40）以相邻的非连续方式与支撑体（41）以空间 在两个相邻层（40）之间，在每个这些功能化层上沉积校准的粘合剂滴（43），将应变基底（44）转移到这些粘合剂层上，由此形成的组件的部分被单数化为 产生结合到应变表面的芯片（45）。 本发明还涉及一种通过衬底在不同膨胀系数的材料中使半导体读取电路处于应变状态的方法。

公开(公告)号：US20080107877A1

公开(公告)日：2008-05-08

申请号：US11661047

申请日：2005-09-25

Applicant: Francois Marion ,  Cecile Davoine

Inventor： Francois Marion ,  Cecile Davoine

IPC: B32B3/00 ,  B44C1/22

CPC classification number: G03F7/0002 ,  B81C1/0046 ,  B82Y10/00 ,  B82Y40/00 ,  H05K3/04 ,  H05K3/062 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/0108 ,  H05K2203/0113 ,  Y10T428/12222 ,  Y10T428/12354 ,  Y10T428/12382 ,  Y10T428/125 ,  Y10T428/12507 ,  Y10T428/12708 ,  Y10T428/12889 ,  Y10T428/24917

Abstract: The invention concerns a nanoprinted device comprising point shaped metallic patterns, in which. each metallic pattern has a bilayer structure controlled in hardness and in chemical properties comprising a lower layer (30) constituting the base of the point and an upper layer (31) constituting the point itself.

Abstract translation: 本发明涉及包含点状金属图案的纳米印刷装置，其中。 每个金属图案具有控制硬度和化学特性的双层结构，包括构成点的底部的下层（30）和构成点本身的上层（31）。

公开(公告)号：US07759261B2

公开(公告)日：2010-07-20

申请号：US11576056

申请日：2004-10-13

Applicant: Francois Marion ,  Philippe Rambaud ,  Lydie Mathieu

Inventor： Francois Marion ,  Philippe Rambaud ,  Lydie Mathieu

IPC: H01L21/31

CPC classification number: H01L25/50 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for obtaining layers defined on a hybrid circuit. The hybrid circuit including a substrate and at least one elementary circuit that includes a first facet and a second facet, being hybridized via the second facet to a facet of the substrate. This facet of the substrate and each elementary circuit are coated with a first layer, the first layer is removed from the first facet of the elementary circuit, the first facet and the subsisting part of the first layer are coated with a second layer, and the subsisting part and the second layer covering it are removed. Such a method may, for example, find application to obtaining an antireflection or metal layer on a chip.

Abstract translation: 一种用于获得在混合电路上定义的层的方法。 所述混合电路包括基板和至少一个元件电路，所述至少一个元件电路包括第一刻面和第二刻面，其经由所述第二刻面与所述基板的刻面杂交。 衬底和每个基本电路的这个面被涂覆有第一层，第一层从基本电路的第一面移除，第一层和第一层的存在部分涂覆有第二层，并且 存放部分和覆盖它的第二层被去除。 例如，这种方法可以应用于获得芯片上的抗反射或金属层。

公开(公告)号：US20090162657A1

公开(公告)日：2009-06-25

申请号：US12254484

申请日：2008-10-20

Applicant: Laurent Grenouillet ,  Jonathan Garcia ,  Francois Marion ,  Nicolas Olivier ,  Marion Perrin

Inventor： Laurent Grenouillet ,  Jonathan Garcia ,  Francois Marion ,  Nicolas Olivier ,  Marion Perrin

IPC: B32B15/02 ,  B22F9/00

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/11001 ,  H01L2224/114 ,  H01L2224/1152 ,  H01L2224/1161 ,  H01L2224/11622 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13101 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01052 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01065 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07811 ,  H01L2924/10329 ,  H05K3/323 ,  H05K3/3478 ,  Y10T428/2982 ,  H01L2924/00014 ,  H01L2924/01048 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

Abstract: The invention relates to a method for manufacturing chips composed of at least one electrically conductive material. Such a method comprises the following steps: deposition, on a support, of an alloy comprising at least the electrically conductive material and a second material; exposure of the alloy to plasma etching, in order to cause the desorption of the materials of the alloy not forming part of the composition of the chips, that is at least the second material but not the electrically conductive material; formation of chips composed of at least said electrically conductive material.

Abstract translation: 本发明涉及一种制造由至少一种导电材料构成的芯片的方法。 这种方法包括以下步骤：在载体上沉积至少包含导电材料和第二材料的合金; 将合金暴露于等离子体蚀刻中，以便导致合金材料的解吸不形成芯片组成的一部分，即至少是第二材料而不是导电材料; 形成由至少所述导电材料构成的芯片。

公开(公告)号：US20070048905A1

公开(公告)日：2007-03-01

申请号：US11503847

申请日：2006-08-14

Applicant: Francois Marion

Inventor： Francois Marion

IPC: H01L21/00

CPC classification number: B81C1/00269 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/73103 ,  H01L2224/73203 ,  H05K3/3436 ,  H05K2201/094 ,  H05K2201/10666 ,  H05K2203/1147 ,  Y02P70/613 ,  H01L2924/00012

Abstract: A method for encapsulating a component by using a chamber in which there is a vacuum or controlled atmosphere, positioning a continuous sealing seam made of a metal or a metal alloy on a wettable surface previously placed on a substrate including at least one component and extending around the periphery of the component(s), positioning a package on the sealing seam, and raising the temperature inside the chamber to fuse the material that constitutes the sealing seam, thereby causing the package to drop onto the substrate and form a leaktight, hermetic seal between the package and the substrate.

Abstract translation: 一种通过使用其中存在真空或受控气氛的室来封装部件的方法，将由金属或金属合金制成的连续密封接缝定位在预先放置在包括至少一个部件并且围绕 组件的周边，将封装定位在密封接缝上，并且提高室内的温度以熔化构成密封接缝的材料，从而使封装落到基板上并形成密封的气密密封 在封装和基板之间。