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公开(公告)号:US20080128879A1
公开(公告)日:2008-06-05
申请号:US11679094
申请日:2007-02-26
申请人: Hem Takiar , Shrikar Bhagath , Chin-Tien Chiu , Ong King Hoo
发明人: Hem Takiar , Shrikar Bhagath , Chin-Tien Chiu , Ong King Hoo
IPC分类号: H01L25/065
CPC分类号: H01L25/0657 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/85 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4554 , H01L2224/4569 , H01L2224/48091 , H01L2224/48227 , H01L2224/48471 , H01L2224/49175 , H01L2224/73265 , H01L2224/83191 , H01L2224/85186 , H01L2224/8592 , H01L2224/92 , H01L2224/92247 , H01L2225/0651 , H01L2225/06575 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01052 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2224/78 , H01L2924/00 , H01L2924/00012
摘要: A low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first and second semiconductor die are separated by a low profile intermediate adhesive layer in which the wire bond loops from the first semiconductor die are embedded. After the intermediate layer is applied, the second semiconductor die may be stacked on top of the intermediate layer. A dielectric layer may be formed on a back surface of the second semiconductor die. As the back side of the second semiconductor die is an electrical insulator, the intermediate layer need not space the wire bond loops from the second semiconductor die as in the prior art, and the apex of bond wires may come into contact with the dielectric layer. The intermediate layer may thus be made thinner in comparison to conventional stacked semiconductor die configurations.
摘要翻译: 公开了一种低剖面半导体封装,其包括至少安装到衬底的第一和第二层叠半导体管芯。 第一半导体管芯和第二半导体管芯由嵌入第一半导体管芯的引线接合环路的低剖面中间粘合剂层分开。 在施加中间层之后,第二半导体管芯可以堆叠在中间层的顶部上。 可以在第二半导体管芯的后表面上形成电介质层。 由于第二半导体管芯的背面是电绝缘体,所以如现有技术那样,中间层不需要与第二半导体管芯的引线接合环空间,并且接合线的顶点可能与介电层接触。 因此,与传统的堆叠半导体管芯配置相比,中间层可以被制成更薄。
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公开(公告)号:US20080131998A1
公开(公告)日:2008-06-05
申请号:US11566097
申请日:2006-12-01
申请人: Hem Takiar , Shrikar Bhagath , Chin-Tien Chiu , Ong King Hoo
发明人: Hem Takiar , Shrikar Bhagath , Chin-Tien Chiu , Ong King Hoo
IPC分类号: H01L21/768
CPC分类号: H01L25/0657 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L2224/2919 , H01L2224/2929 , H01L2224/29299 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4554 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48175 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/48599 , H01L2224/48699 , H01L2224/48992 , H01L2224/49175 , H01L2224/73265 , H01L2224/8314 , H01L2224/83191 , H01L2224/83192 , H01L2224/83194 , H01L2224/8385 , H01L2224/83856 , H01L2224/83862 , H01L2224/83874 , H01L2224/85186 , H01L2224/8592 , H01L2224/92 , H01L2224/92247 , H01L2225/0651 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2224/78 , H01L2924/00 , H01L2924/00012 , H01L2924/01006 , H01L2224/85399 , H01L2224/05599
摘要: A low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first and second semiconductor die are separated by a low profile intermediate adhesive layer in which the wire bond loops from the first semiconductor die are embedded. After the intermediate layer is applied, the second semiconductor die may be stacked on top of the intermediate layer. A dielectric layer may be formed on a back surface of the second semiconductor die. As the back side of the second semiconductor die is an electrical insulator, the intermediate layer need not space the wire bond loops from the second semiconductor die as in the prior art, and the apex of bond wires may come into contact with the dielectric layer. The intermediate layer may thus be made thinner in comparison to conventional stacked semiconductor die configurations.
摘要翻译: 公开了一种低剖面半导体封装,其包括至少安装到衬底的第一和第二层叠半导体管芯。 第一半导体管芯和第二半导体管芯由嵌入第一半导体管芯的引线接合环路的低剖面中间粘合剂层分开。 在施加中间层之后,第二半导体管芯可以堆叠在中间层的顶部上。 可以在第二半导体管芯的后表面上形成电介质层。 由于第二半导体管芯的背面是电绝缘体,所以如现有技术那样,中间层不需要与第二半导体管芯的引线接合环空间,并且接合线的顶点可能与介电层接触。 因此,与传统的堆叠半导体管芯配置相比,中间层可以被制成更薄。
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公开(公告)号:US20120279651A1
公开(公告)日:2012-11-08
申请号:US13257285
申请日:2011-05-05
申请人: Wei Gu , Zhong Lu , Shrikar Bhagath , Chin-Tien Chiu , Hem Takiar , XiangYang Liu
发明人: Wei Gu , Zhong Lu , Shrikar Bhagath , Chin-Tien Chiu , Hem Takiar , XiangYang Liu
CPC分类号: H01L24/83 , B05B12/20 , B05B13/02 , B05B14/00 , H01L21/56 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/743 , H01L24/92 , H01L24/97 , H01L2224/0332 , H01L2224/0345 , H01L2224/0346 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/06155 , H01L2224/2732 , H01L2224/27418 , H01L2224/29013 , H01L2224/29014 , H01L2224/29034 , H01L2224/2919 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2224/83192 , H01L2224/8385 , H01L2224/83856 , H01L2224/97 , H01L2225/0651 , H01L2225/06568 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/12042 , H01L2924/1431 , H01L2924/1438 , H01L2924/181 , Y10T156/1092 , Y10T428/24802 , H01L2224/83 , H01L2924/00012 , H01L2224/85 , H01L2224/92247 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: A system and method are disclosed for applying a die attach epoxy to substrates on a panel of substrates. The system includes a window clamp having one or more windows through which the epoxy may be applied onto the substrate panel. The size and shape of the one or more windows correspond to the size and shape of the area on the substrate to receive the die attach epoxy. Once the die attach epoxy is sprayed onto the substrate through the windows of the window clamp, the die may be affixed to the substrate and the epoxy cured in one or more curing steps. The system may further include a clean-up follower for cleaning epoxy off of the window clamp, and a window cleaning mechanism for cleaning epoxy off of the sidewalls of the windows of the window clamp.
摘要翻译: 公开了一种用于将芯片附着环氧树脂施加到基板面板上的基板的系统和方法。 该系统包括具有一个或多个窗口的窗口夹具,环氧树脂可以通过该窗口施加到基板面板上。 一个或多个窗口的尺寸和形状对应于基板上的区域的尺寸和形状以接收管芯附着环氧树脂。 一旦模具附着环氧树脂通过窗口夹具的窗口喷涂到基材上,模具可以固定在基材上,环氧树脂在一个或多个固化步骤中固化。 该系统还可以包括用于清洁窗夹的环氧树脂的清理跟随器,以及用于从窗夹的窗口侧壁清洁环氧树脂的窗清洁机构。
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公开(公告)号:US07485501B2
公开(公告)日:2009-02-03
申请号:US11265337
申请日:2005-11-02
申请人: Hem Takiar , Shrikar Bhagath , Chin-Tien Chiu
发明人: Hem Takiar , Shrikar Bhagath , Chin-Tien Chiu
IPC分类号: H01L21/44
CPC分类号: H01L21/561 , H01L21/565 , H01L24/97 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/12041 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/19043 , H01L2924/00014 , H01L2924/00
摘要: A method is disclosed for forming semiconductor packages by a process of punching and cutting the packages from a panel of integrated circuits. During an encapsulation process for encapsulating the packages in a molding compound, portions of the panel may be left free of molding compound. Portions of the panel left free of molding compound may subsequently be punched from the panel. These punched areas may define chamfers, notches or a variety of other curvilinear, rectilinear or irregular shapes in the outer edges of the finished semiconductor package. After the panel is punched, the integrated circuits may be singulated. By punching areas from the panel, and then cutting along straight edges, a simple, effective and cost efficient method is disclosed for obtaining finished semiconductor packages of a variety of desired shapes.
摘要翻译: 公开了一种用于通过从集成电路板冲压和切割封装件的工艺来形成半导体封装件的方法。 在将包装封装在模塑料中的封装过程中,面板的部分可以不含模塑料。 随后可以从面板冲压出没有模塑料的板的部分。 这些冲压区域可以在完成的半导体封装的外边缘中限定倒角,凹口或各种其它曲线,直线形或不规则形状。 在打孔面板之后,可以将集成电路分割。 通过从面板冲压区域,然后沿直边切割,公开了一种简单,有效和成本有效的方法来获得各种期望形状的成品半导体封装。
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公开(公告)号:US07967184B2
公开(公告)日:2011-06-28
申请号:US11280419
申请日:2005-11-16
申请人: Chih-Chin Liao , Ken Jian Ming Wang , Han-Shiao Chen , Chin-Tien Chiu , Jack Chang Chien , Shrikar Bhagath , Cheemen Yu , Hem Takiar
发明人: Chih-Chin Liao , Ken Jian Ming Wang , Han-Shiao Chen , Chin-Tien Chiu , Jack Chang Chien , Shrikar Bhagath , Cheemen Yu , Hem Takiar
IPC分类号: B23K31/02
CPC分类号: H05K1/111 , H01L2224/48091 , H01L2224/48227 , H05K3/3421 , H05K3/3442 , H05K3/3452 , H05K2201/09427 , H05K2201/09663 , H05K2201/0989 , H05K2201/099 , H05K2201/10636 , H05K2201/10689 , H05K2201/10727 , Y02P70/611 , Y02P70/613 , H01L2924/00014
摘要: A semiconductor package having a low profile is disclosed. In embodiments, a surface mounted component may be mounted directly to the core of the semiconductor package substrate, so that there is no conductive layer, plating layers or solder paste between the component and the substrate core. The surface mounted component may be any type of component which may be surface mounted on a substrate according to an SMT process, including for example passive components and various packaged semiconductors.
摘要翻译: 公开了一种具有低轮廓的半导体封装。 在实施例中,表面安装部件可以直接安装到半导体封装基板的芯部,使得在部件和基板芯之间不存在导电层,镀层或焊膏。 表面安装部件可以是根据SMT工艺可以表面安装在基板上的任何类型的部件,包括例如无源部件和各种封装半导体。
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公开(公告)号:US20070099340A1
公开(公告)日:2007-05-03
申请号:US11265337
申请日:2005-11-02
申请人: Hem Takiar , Shrikar Bhagath , Chin-Tien Chiu
发明人: Hem Takiar , Shrikar Bhagath , Chin-Tien Chiu
IPC分类号: H01L21/00
CPC分类号: H01L21/561 , H01L21/565 , H01L24/97 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/12041 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/19043 , H01L2924/00014 , H01L2924/00
摘要: A method is disclosed for forming semiconductor packages by a process of punching and cutting the packages from a panel of integrated circuits. During an encapsulation process for encapsulating the packages in a molding compound, portions of the panel may be left free of molding compound. Portions of the panel left free of molding compound may subsequently be punched from the panel. These punched areas may define chamfers, notches or a variety of other curvilinear, rectilinear or irregular shapes in the outer edges of the finished semiconductor package. After the panel is punched, the integrated circuits may be singulated. By punching areas from the panel, and then cutting along straight edges, a simple, effective and cost efficient method is disclosed for obtaining finished semiconductor packages of a variety of desired shapes.
摘要翻译: 公开了一种用于通过从集成电路板冲压和切割封装件的工艺来形成半导体封装件的方法。 在将包装封装在模塑料中的封装过程中,面板的部分可以不含模塑料。 随后可以从面板冲压出没有模塑料的板的部分。 这些冲压区域可以在完成的半导体封装的外边缘中限定倒角,凹口或各种其它曲线,直线形或不规则形状。 在打孔面板之后,可以将集成电路分割。 通过从面板冲压区域,然后沿直边切割,公开了一种简单,有效和成本有效的方法来获得各种期望形状的成品半导体封装。
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7.
公开(公告)号:US20070163109A1
公开(公告)日:2007-07-19
申请号:US11321426
申请日:2005-12-29
申请人: Hem Takiar , Manickam Thavarajah , Ken Wang , Chih-Chin Liao , Andre McKenzie , Shrikar Bhagath , Han-Shiao Chen , Chin-Tien Chiu
发明人: Hem Takiar , Manickam Thavarajah , Ken Wang , Chih-Chin Liao , Andre McKenzie , Shrikar Bhagath , Han-Shiao Chen , Chin-Tien Chiu
IPC分类号: H01R43/00
CPC分类号: H01L23/544 , H01L21/4857 , H01L21/50 , H01L21/561 , H01L23/49565 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2223/54486 , H01L2224/2929 , H01L2224/293 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83801 , H01L2224/83851 , H01L2224/85 , H01L2224/97 , H01L2225/06568 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/0781 , H01L2924/12041 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , Y10T29/49117 , H01L2924/00012 , H01L2924/3512 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: A strip on which a plurality of integrated circuit package outlines may be fabricated within a plurality of process tools. The strip includes one or more fiducial notches and/or guide pin notches formed in an outer edge of the strip. The one or more fiducial and/or guide pin notches allow a position of the strip to be identified within at least one process tool of the plurality of process tools. By forming the notches in the outer periphery of the strip, the usable area on the strip on which integrated circuit package outlines may be formed is increased. The strip may alternatively include conventional fiducial and/or guide pin holes, with the molding compound applied at least partially around the holes on one or more sides of the strip. The strip may further alternatively include fiducial holes filled with a translucent material that provides stability to the strip while allowing the strip to be used with an optical recognition sensor.
摘要翻译: 其上可以在多个处理工具内制造多个集成电路封装轮廓的条带。 带材包括形成在带的外边缘中的一个或多个基准凹口和/或导向销切口。 一个或多个基准和/或引导销凹口允许在多个处理工具的至少一个处理工具内识别条带的位置。 通过在带的外周形成切口,可以形成集成电路封装轮廓的带上的可用区域。 条带可替代地包括常规的基准和/或引导销孔,模制化合物至少部分地围绕带的一侧或多侧上的孔施加。 条带还可以包括填充有半透明材料的基准孔,其为条带提供稳定性,同时允许条带与光学识别传感器一起使用。
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公开(公告)号:US20070108257A1
公开(公告)日:2007-05-17
申请号:US11280419
申请日:2005-11-16
申请人: Chih-Chin Liao , Ken Wang , Han-Shiao Chen , Chin-Tien Chiu , Jack Chien , Shrikar Bhagath , Cheemen Yu , Hem Takiar
发明人: Chih-Chin Liao , Ken Wang , Han-Shiao Chen , Chin-Tien Chiu , Jack Chien , Shrikar Bhagath , Cheemen Yu , Hem Takiar
CPC分类号: H05K1/111 , H01L2224/48091 , H01L2224/48227 , H05K3/3421 , H05K3/3442 , H05K3/3452 , H05K2201/09427 , H05K2201/09663 , H05K2201/0989 , H05K2201/099 , H05K2201/10636 , H05K2201/10689 , H05K2201/10727 , Y02P70/611 , Y02P70/613 , H01L2924/00014
摘要: A semiconductor package having a low profile is disclosed. In embodiments, a surface mounted component may be mounted directly to the core of the semiconductor package substrate, so that there is no conductive layer, plating layers or solder paste between the component and the substrate core. The surface mounted component may be any type of component which may be surface mounted on a substrate according to an SMT process, including for example passive components and various packaged semiconductors.
摘要翻译: 公开了一种具有低轮廓的半导体封装。 在实施例中,表面安装部件可以直接安装到半导体封装基板的芯部,使得在部件和基板芯之间不存在导电层,镀层或焊膏。 表面安装部件可以是根据SMT工艺可以表面安装在基板上的任何类型的部件,包括例如无源部件和各种封装半导体。
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公开(公告)号:US08637978B2
公开(公告)日:2014-01-28
申请号:US13235781
申请日:2011-09-19
CPC分类号: G06K19/07745 , G06K19/07732 , G11C5/04 , H01L21/565 , H01L23/3107 , H01L24/48 , H01L24/97 , H01L25/0657 , H01L25/16 , H01L2223/5442 , H01L2223/54433 , H01L2223/54473 , H01L2223/54486 , H01L2224/32145 , H01L2224/48225 , H01L2224/48227 , H01L2224/97 , H01L2225/0651 , H01L2225/06568 , H01L2924/00014 , H01L2924/01322 , H01L2924/12041 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15312 , H01L2924/15313 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H05K1/181 , H05K3/0052 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00
摘要: A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.
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公开(公告)号:US20070004094A1
公开(公告)日:2007-01-04
申请号:US11171095
申请日:2005-06-30
申请人: Hem Takiar , Shrikar Bhagath , Ken Wang
发明人: Hem Takiar , Shrikar Bhagath , Ken Wang
IPC分类号: H01L21/58
CPC分类号: H01L23/49855 , H01L23/49838 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/01322 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H05K1/0224 , H05K1/0253 , H05K1/0271 , H05K2201/09681 , H05K2201/09781 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: A dummy circuit pattern is disclosed on a surface of a substrate for a semiconductor package, the dummy circuit pattern including straight line segments having a length controlled so as not to generate stresses within the line segments above a desired stress. The dummy circuit pattern may be formed of lines, or contiguous or spaced polygons, such as hexagons. Portions of the dummy circuit pattern may also be formed with an orientation, size and position that are randomly selected.
摘要翻译: 公开了用于半导体封装的衬底的表面上的虚拟电路图案,该虚拟电路图案包括直线段,其长度受到控制,以便不在所述线段内产生高于所需应力的应力。 虚拟电路图案可以由线或邻接的或间隔开的多边形(例如六边形)形成。 虚拟电路图案的部分也可以形成为随机选择的取向,尺寸和位置。
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