公开(公告)号：US5053480A

公开(公告)日：1991-10-01

申请号：US503104

申请日：1990-04-02

申请人： Noriaki Koto ,  Toyohiko Abe ,  Hideo Suzuki ,  Kanji Otsuka

发明人： Noriaki Koto ,  Toyohiko Abe ,  Hideo Suzuki ,  Kanji Otsuka

IPC分类号： C08G73/00 ,  C08G73/10

CPC分类号： C08G73/105 ,  C08G73/10 ,  C08G73/1064

摘要： A polyimide resin composed essentially of repeating units represented by the general formula: ##STR1## where R is a divalent aromatic hydrocarbon radical.

摘要翻译： 基本上由以下通式表示的重复单元组成的聚酰亚胺树脂：其中R是二价芳族烃基。

公开(公告)号：US08217466B2

公开(公告)日：2012-07-10

申请号：US11990491

申请日：2006-08-01

申请人： Kanji Otsuka ,  Fumio Mizuno ,  Munekazu Takano ,  Tamotsu Usami

发明人： Kanji Otsuka ,  Fumio Mizuno ,  Munekazu Takano ,  Tamotsu Usami

IPC分类号： H01L21/70

CPC分类号： H01L27/1211 ,  H01L21/823493 ,  H01L27/0705 ,  H01L29/66795 ,  H01L29/785

摘要： Disclosed is a semiconductor device wherein the switching speed of a transistor is increased. Specifically disclosed is a semiconductor device comprising a semiconductor layer formed on a part of an insulating layer, a first transistor formed on a lateral face of the semiconductor layer and having a first gate insulating film, a first gate electrode and two first impurity layers forming a source and a drain, and a second transistor formed on another lateral face of the semiconductor layer and having a second gate insulating film, a second gate electrode and two second impurity layers forming a source and a drain.

摘要翻译： 公开了一种半导体器件，其中晶体管的开关速度增加。 具体公开了一种半导体器件，包括形成在绝缘层的一部分上的半导体层，形成在半导体层的侧面上的第一晶体管，并具有第一栅极绝缘膜，第一栅电极和两个第一杂质层， 源极和漏极，以及形成在所述半导体层的另一个侧面上并具有第二栅极绝缘膜，第二栅极电极和形成源极和漏极的两个第二杂质层的第二晶体管。

公开(公告)号：US07804111B2

公开(公告)日：2010-09-28

申请号：US12083573

申请日：2006-10-10

申请人： Kanji Otsuka ,  Munekazu Takano ,  Fumio Mizuno ,  Saburo Yokokura ,  Tsuneo Ito ,  Yuko Tanba ,  Yutaka Akiyama

发明人： Kanji Otsuka ,  Munekazu Takano ,  Fumio Mizuno ,  Saburo Yokokura ,  Tsuneo Ito ,  Yuko Tanba ,  Yutaka Akiyama

IPC分类号： H01L29/94

CPC分类号： H03K5/156 ,  H01L23/642 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/19041 ,  H01L2924/19051 ,  H01L2924/30107 ,  H01L2924/3011 ,  H03K2005/00026 ,  H03K2217/0018 ,  H04L25/085 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The object of the invention is to provide a semiconductor device including signal-transmission interconnections preferable for transmitting high frequency signal and capability to adjust characteristics of the above signal-transmission interconnections. A semiconductor device according to the present invention consists of a signal-transmission interconnection 20 for transmission of signals, a MOS capacitance element 10 having a gate electrode connected to the signal-transmission interconnection 20, a first voltage-applying interconnection 30 connected to a source and a drain of the MOS capacitance element 10 and applying a voltage to the source and the drain of the MOS capacitance element 10, a second voltage-applying interconnection 40 connected to a well of the MOS capacitance element 10, and applying a voltage to the well of said first MOS capacitance element 10. Jitters occurring in the signal-transmission interconnection 20 can be adjusted by adjusting each of voltages of the first voltage-applying interconnection 30 and the second voltage-applying interconnection 40.

摘要翻译： 本发明的目的是提供一种半导体器件，其包括优选用于传输高频信号的信号传输互连和调整上述信号传输互连特性的能力。 根据本发明的半导体器件包括用于传输信号的信号传输互连20，具有连接到信号传输互连20的栅电极的MOS电容元件10，连接到源的第一施加电压互连30 和MOS电容元件10的漏极，并向MOS电容元件10的源极和漏极施加电压，连接到MOS电容元件10的阱的第二施加电压互连40，并向 可以通过调节第一施加电压互连30和第二施加电压互连40的每个电压来调节发生在信号传输互连20中的抖动。

公开(公告)号：US20090096029A1

公开(公告)日：2009-04-16

申请号：US11990491

申请日：2006-08-01

申请人： Kanji Otsuka ,  Fumio Mizuno ,  Munekazu Takano ,  Tamotsu Usami

发明人： Kanji Otsuka ,  Fumio Mizuno ,  Munekazu Takano ,  Tamotsu Usami

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L27/1211 ,  H01L21/823493 ,  H01L27/0705 ,  H01L29/66795 ,  H01L29/785

摘要： Disclosed is a semiconductor device wherein the switching speed of a transistor is increased. Specifically disclosed is a semiconductor device comprising a semiconductor layer formed on a part of an insulating layer, a first transistor formed on a lateral face of the semiconductor layer and having a first gate insulating film, a first gate electrode and two first impurity layers forming a source and a drain, and a second transistor formed on another lateral face of the semiconductor layer and having a second gate insulating film, a second gate electrode and two second impurity layers forming a source and a drain.

摘要翻译： 公开了一种半导体器件，其中晶体管的开关速度增加。 具体公开了一种半导体器件，包括形成在绝缘层的一部分上的半导体层，形成在半导体层的侧面上的第一晶体管，并具有第一栅极绝缘膜，第一栅电极和两个第一杂质层， 源极和漏极，以及形成在所述半导体层的另一个侧面上并具有第二栅极绝缘膜，第二栅极电极和形成源极和漏极的两个第二杂质层的第二晶体管。

公开(公告)号：US5191224A

公开(公告)日：1993-03-02

申请号：US627881

申请日：1990-12-13

申请人： Masanori Tazunoki ,  Hiromitsu Mishimagi ,  Makoto Homma ,  Toshiyuki Sakuta ,  Hisashi Nakamura ,  Keiji Sasaki ,  Minoru Enomoto ,  Toshihiko Satoh ,  Kunizo Sahara ,  Shigeo Kuroda ,  Kanji Otsuka ,  Masao Kawamura ,  Hinoko Kurosawa ,  Kazuya Ito

发明人： Masanori Tazunoki ,  Hiromitsu Mishimagi ,  Makoto Homma ,  Toshiyuki Sakuta ,  Hisashi Nakamura ,  Keiji Sasaki ,  Minoru Enomoto ,  Toshihiko Satoh ,  Kunizo Sahara ,  Shigeo Kuroda ,  Kanji Otsuka ,  Masao Kawamura ,  Hinoko Kurosawa ,  Kazuya Ito

IPC分类号： H01L23/14 ,  H01L23/32 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07

CPC分类号： H01L23/147 ,  H01L23/32 ,  H01L23/5385 ,  H01L25/0652 ,  H01L25/073 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/3025

摘要： To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way that a memory system layout can be precisely realized and a precise through hole can be formed. Moreover, other chips are fixed on the wafer so as to achieve furthermore the high packaging density.

摘要翻译： 为了实现全尺寸晶片存储器或晶片级积分存储器系统的更高的封装密度和一个晶片级，晶片以预定的间隔彼此垂直堆叠。 改进了封装技术，使得可以精确地实现存储器系统布局并且可以形成精确的通孔。 此外，其他芯片固定在晶片上，从而进一步实现高封装密度。

公开(公告)号：US5107329A

公开(公告)日：1992-04-21

申请号：US315608

申请日：1989-02-27

申请人： Takayuki Okinaga ,  Kanji Otsuka ,  Hiroshi Akasaki

发明人： Takayuki Okinaga ,  Kanji Otsuka ,  Hiroshi Akasaki

IPC分类号： H01L23/50 ,  H01L23/057 ,  H01L23/498 ,  H05K1/18 ,  H05K3/30 ,  H05K3/34

CPC分类号： H01L23/49827 ,  H01L23/057 ,  H01L23/49811 ,  H05K3/303 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/181 ,  H05K2201/10568 ,  H05K2201/10659 ,  H05K2201/10704 ,  H05K2203/167 ,  H05K3/3426 ,  H05K3/3447 ,  Y02P70/613

摘要： A semiconductor device of pin-grid array (PGA) type, which is adapted for surface-mounting on a printed circuit board, has lead pins arranged in a grid and standing perpendicularly on a base of the semiconductor device. In addition, a few pins are provided which are longer than said lead pins in said grid. When the device is placed on the printed circuit board for mounting, the longer pins are inserted into through-holes which are respectively formed in the printed circuit board to correspond to the position of the longer pins of the device. Thus, the tip of the lead pins are accurately positioned on the top of lands on the printed circuit board, respectively, and the lead pins do not get out of position during the mounting operation.

摘要翻译： 针对栅极阵列（PGA）类型的半导体器件适用于表面安装在印刷电路板上，具有布置成格栅并垂直于半导体器件的基座垂直放置的引线引脚。 此外，提供了比所述电网中的所述引线引脚长的几个引脚。 当将装置放置在印刷电路板上用于安装时，较长的针被插入到分别形成在印刷电路板中的通孔中，以对应于装置的较长销的位置。 因此，引脚的尖端分别精确地定位在印刷电路板上的焊盘的顶部，并且引线引脚在安装操作期间不会脱离位置。

公开(公告)号：US5067007A

公开(公告)日：1991-11-19

申请号：US645357

申请日：1991-01-24

申请人： Kanji Otsuka ,  Masao Kato ,  Takashi Kumagai ,  Mitsuo Usami ,  Shigeo Kuroda ,  Kunizo Sahara ,  Takeo Yamada ,  Seiji Miyamoto ,  Yuuji Shirai ,  Takayuki Okinaga ,  Kazutoshi Kubo ,  Hiroshi Tachi ,  Masayuki Kawashima

发明人： Kanji Otsuka ,  Masao Kato ,  Takashi Kumagai ,  Mitsuo Usami ,  Shigeo Kuroda ,  Kunizo Sahara ,  Takeo Yamada ,  Seiji Miyamoto ,  Yuuji Shirai ,  Takayuki Okinaga ,  Kazutoshi Kubo ,  Hiroshi Tachi ,  Masayuki Kawashima

IPC分类号： H01L23/50 ,  H01L23/433 ,  H01L23/495 ,  H01L23/498 ,  H05K3/34

CPC分类号： H01L23/49555 ,  H01L23/433 ,  H01L23/49579 ,  H01L23/49811 ,  H05K3/3426 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K2201/0308 ,  H05K2201/10318 ,  H05K2201/10681 ,  H05K2201/10704 ,  H05K2201/10909 ,  H05K2201/2081 ,  Y02P70/613

摘要： Attempts have been made to increase the number of pins of packages accompanying the trend toward fabricating integrated circuits highly densely and in smaller sizes. The present invention provides technology for improving reliability in fabricating packages of the surface-mounted type that have increased number of pins. That is, when the packages are mounted on the wiring substrate, the lead pins that receive load from the axial direction exhibit bending strength which is smaller than the junction strength of solder at the junction portions. To achieve this object, the lead pins are made of a material having large resiliency such as a fiber-reinforced material, a transformation pseudo elastic material, an ultra-high tension material, or a heat-resistant ultra-high tension material.

摘要翻译： 随着制造高密度和小尺寸集成电路的趋势，已经尝试增加封装引脚的数量。 本发明提供了提高具有增加的引脚数的表面安装型封装的可靠性的技术。 也就是说，当封装被安装在布线基板上时，从轴向接收负载的引线销显示出小于接合部处的焊料的接合强度的弯曲强度。 为了实现该目的，引脚由具有大弹性的材料制成，例如纤维增强材料，变形假弹性材料，超高张力材料或耐热超高张力材料。

公开(公告)号：US5032895A

公开(公告)日：1991-07-16

申请号：US510844

申请日：1990-04-18

申请人： Osamu Horiuchi ,  Gen Murakami ,  Hiromichi Suzuki ,  Hajime Hasebe ,  Kanji Otsuka ,  Yuuji Shirai ,  Takayuki Okinaga ,  Takashi Emata

发明人： Osamu Horiuchi ,  Gen Murakami ,  Hiromichi Suzuki ,  Hajime Hasebe ,  Kanji Otsuka ,  Yuuji Shirai ,  Takayuki Okinaga ,  Takashi Emata

IPC分类号： H01L21/60 ,  H01L23/495 ,  H01L23/498

CPC分类号： H01L23/49527 ,  H01L23/49537 ,  H01L23/49558 ,  H01L23/49861 ,  H01L24/49 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107

摘要： A semiconductor device comprising the fact that a semiconductor pellet is arranged on a substantially central part of a film base in which a metal plate is overlaid with an insulating member, while inner leads are arranged on a peripheral part of the film base in a state in which they are electrically isolated from the metal plate of the film base, and that external terminals for a power source among external terminals of the semiconductor pellet and middle parts of the metal plate of the film base, and inner leads for the power source among the inner leads and peripheral parts of the metal plate are electrically connected by pieces of bonding wire, respectively.

摘要翻译： 一种半导体器件，包括半导体芯片布置在薄膜基座的大致中央部分，其中金属板覆盖有绝缘构件，而内部引线以薄膜基底的周边部分布置在 它们与膜基底的金属板电隔离，并且在半导体芯片的外部端子和膜基底的金属板的中间部分之间的电源的外部端子和用于电源的内部引线 金属板的内部引线和外围部分分别通过接合线电连接。

公开(公告)号：US4886573A

公开(公告)日：1989-12-12

申请号：US87021

申请日：1987-08-19

申请人： Hiroshi Watanabe ,  Osamu Miura ,  Kunio Miyazaki ,  Shunichi Numata ,  Kanji Otsuka

发明人： Hiroshi Watanabe ,  Osamu Miura ,  Kunio Miyazaki ,  Shunichi Numata ,  Kanji Otsuka

IPC分类号： H01L21/3205 ,  H01L21/027 ,  H01L21/306 ,  H01L21/312 ,  H05K3/02 ,  H05K3/04 ,  H05K3/06 ,  H05K3/46

CPC分类号： H05K3/048 ,  H01L21/0272 ,  H01L21/312

摘要： In a process for forming a wiring conductor of Cu, Al, Au or the like on a wiring substrate, polyimide-based resin having the following unit structural formula is used as a lift-off material. ##STR1## wherein R.sub.1 : ##STR2## R.sub.2 : ##STR3## n is an integer of 15,000 to 30,000. This lift-off material has very good etching susceptibility and can be selectively lifted off with an etching solution of a mixture of hydrazine and ethylene diamine from a lower polyimide layer having R.sub.1 : ##STR4## R.sub.2 : ##STR5## .

摘要翻译： 在布线基板上形成Cu，Al，Au等布线导体的方法中，使用具有下列单元结构式的聚酰亚胺系树脂作为剥离材料。 其中R1： R2： n是15,000至30,000的整数。 这种剥离材料具有非常好的蚀刻敏感性，并且可以用来自具有R1：R2的下聚酰亚胺层的肼和乙二胺的混合物的蚀刻溶液选择性地剥离。

公开(公告)号：US4630095A

公开(公告)日：1986-12-16

申请号：US626200

申请日：1984-06-29

申请人： Kanji Otsuka ,  Kunizou Sahara ,  Masao Sekibata ,  Kazumichi Mitsusada ,  Katsumi Ogiue

发明人： Kanji Otsuka ,  Kunizou Sahara ,  Masao Sekibata ,  Kazumichi Mitsusada ,  Katsumi Ogiue

IPC分类号： H01L23/02 ,  H01L23/057 ,  H01L23/26 ,  H01L23/31 ,  H01L23/556 ,  H01L23/10 ,  H01L23/04 ,  H01L23/16 ,  H01L23/30

CPC分类号： H01L23/26 ,  H01L23/057 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/556 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/8592 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/0102 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/16152 ,  H01L2924/1617 ,  H01L2924/16195 ,  H01L2924/3025

摘要： A packaged semiconductor device structure includes a semiconductor chip with an organic material covering thereon. The semiconductor chip is placed in a package and hermetically sealed with a low melting point glass. The organic covering serve to suppress undesirable influence on the semiconductor chip by .alpha.-rays which may be radiated from the package, and a getter material is placed in the package for decreasing undesirable gases in the package which may be emitted by the organic covering during the sealing process.

摘要翻译： 封装的半导体器件结构包括其上覆盖有机材料的半导体芯片。 将半导体芯片放置在封装中并用低熔点玻璃密封。 有机覆盖物用于通过可以从封装辐射的α-射线来抑制对半导体芯片的不期望的影响，并且将吸气剂材料放置在包装中以减少包装中的不期望的气体，这可能由有机覆盖物在 密封过程。