利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

777 条记录 (耗时 0.047 秒)

    Frame structure and semiconductor attach process for use therewith for fabrication of image sensor packages and the like, and resulting packages
    2.
    发明授权
    Frame structure and semiconductor attach process for use therewith for fabrication of image sensor packages and the like, and resulting packages 有权
    用于制造图像传感器封装等的框架结构和半导体附着工艺以及所产生的封装

    公开(公告)号：US07645635B2

    公开(公告)日：2010-01-12

    申请号：US10919604

    申请日：2004-08-16

    申请人： Alan G. Wood ,  Kyle K. Kirby ,  Warren M. Farnworth ,  Salman Akram

    发明人： Alan G. Wood ,  Kyle K. Kirby ,  Warren M. Farnworth ,  Salman Akram

    IPC分类号： H01L21/00

    CPC分类号： H01L27/14618 ,  B33Y80/00 ,  H01L27/14625 ,  H01L2224/48091 ,  H01L2924/00014

    摘要： A semiconductor package such as an image sensor package, and methods for fabrication. A frame structure includes an array of frames, each having an aperture therethrough, into which an image sensor die in combination with a cover glass, filter, lens or other components may be installed in precise mutual alignment. Singulated image sensor dice and other components may be picked and placed into each frame of the frame structure. Alternatively, the frame structure may be configured to be aligned with and joined to a wafer bearing a plurality of image sensor dice, wherein optional, downwardly protruding skirts along peripheries of the frames may be received into kerfs cut along streets between die locations on the wafer, followed by installation of other package components. In either instance, the frame structure in combination with singulated image sensor dice or a joined wafer is singulated into individual image sensor packages. Various external connection approaches may be used for the packages.

    摘要翻译： 诸如图像传感器封装的半导体封装以及制造方法。 框架结构包括每个具有穿过其中的孔的框架阵列，图像传感器与盖玻片，过滤器，透镜或其它部件组合的模具可以精确相互对准地安装在该框架中。 单片图像传感器骰子和其他组件可以被拾取并放置在框架结构的每个帧中。 或者，框架结构可以被配置为与承载多个图像传感器骰子的晶片对准并且连接到其上，其中沿着框架的周边的任选的向下突出的裙边可以被接收到沿着晶片上的模具位置之间沿着街道切割的切口 ，然后安装其他包装组件。 在任一情况下，将帧结构与单独的图像传感器芯片或连接的晶片组合成单独的图像传感器封装。 各种外部连接方法可用于包装。

    Method of forming vias in semiconductor substrates without damaging active regions thereof and resulting structures
    3.
    发明授权
    Method of forming vias in semiconductor substrates without damaging active regions thereof and resulting structures 有权
    在半导体衬底中形成通孔的方法，而不损坏其有效区域和结果

    公开(公告)号：US07598167B2

    公开(公告)日：2009-10-06

    申请号：US11140402

    申请日：2005-05-27

    申请人： Charles M. Watkins ,  Kyle K. Kirby ,  Alan G. Wood ,  Salman Akram ,  Warren M. Farnworth

    发明人： Charles M. Watkins ,  Kyle K. Kirby ,  Alan G. Wood ,  Salman Akram ,  Warren M. Farnworth

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76898

    摘要： Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from the active surface through a conductive element thereon and a portion of the semiconductor substrate underlying the conductive element. The through via may then be completed by laser ablation or drilling from the back surface. In another embodiment, a partial via may be formed by laser ablation or drilling from the back surface of a semiconductor substrate to a predetermined distance therein. The through via may be completed from the active surface by forming a partial via extending through the conductive element and the underlying semiconductor substrate to intersect the laser-drilled partial via. In another embodiment, a partial via may first be formed by ablation or drilling from the back surface of the semiconductor substrate followed by dry etching to complete the through via and expose the underside of the conductive element.

    摘要翻译： 公开了在半导体衬底中形成贯通孔的方法和所得到的结构。 在一个实施例中，通孔可以通过在其上的导电元件和导电元件下面的半导体衬底的一部分从活性表面形成部分通孔而形成通孔。 然后可以通过从后表面的激光烧蚀或钻孔来完成通孔。 在另一个实施例中，部分通孔可以通过激光烧蚀或从半导体衬底的背面钻孔到其中的预定距离来形成。 通孔可以通过形成延伸穿过导电元件和下面的半导体衬底以与激光钻孔的部分通孔相交的部分通孔从活性表面完成。 在另一个实施例中，可以首先通过从半导体衬底的后表面进行烧蚀或钻孔形成部分通孔，然后进行干法蚀刻以完成通孔并暴露导电元件的下侧。

    Probe card for semiconductor wafers having mounting plate and socket
    5.
    发明授权
    Probe card for semiconductor wafers having mounting plate and socket 失效
    带安装板和插座的半导体晶圆探头卡

    公开(公告)号：US07250780B2

    公开(公告)日：2007-07-31

    申请号：US10742729

    申请日：2003-12-19

    申请人： David R. Hembree ,  Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  C. Patrick Doherty ,  Andrew J. Krivy

    发明人： David R. Hembree ,  Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  C. Patrick Doherty ,  Andrew J. Krivy

    IPC分类号： G01R1/073 ,  G01R31/28

    CPC分类号： G01R31/2886

    摘要： A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers. The membrane can be similar to multi layered TAB tape including metal foil conductors attached to a flexible, electrically-insulating, elastomeric tape. The probe card can be configured to contact all of the dice on the wafer at the same time, so that test signals can be electronically applied to selected dice as required.

    摘要翻译： 提供了用于测试半导体晶片的探针卡，以及使用探针卡测试晶片的方法和系统。 探针卡被配置用于与测试电路电气通信的常规测试装置，例如晶片探测器处理器。 探针卡包括具有用于与晶片上的接触位置建立电连通的接触构件的互连基板。 探针卡还包括用于将互连基板物理和电连接到测试装置的膜，以及用于缓冲由测试装置施加在互连基板上的压力的可压缩构件。 互连衬底可以由具有穿透突起的凸起接触构件的硅形成。 或者，接触构件可以形成为用于测试凸起的晶片的凹陷。 膜可以类似于多层TAB带，其包括附接到柔性，电绝缘的弹性体带的金属箔导体。 探针卡可以配置为同时接触晶片上的所有骰子，以便测试信号可以根据需要以电子方式应用于选定的骰子。

    Carrier and system for testing bumped semiconductor components
    9.
    发明授权
    Carrier and system for testing bumped semiconductor components 失效
    用于测试碰撞半导体元件的载体和系统

    公开(公告)号：US06313651B1

    公开(公告)日：2001-11-06

    申请号：US09322724

    申请日：1999-05-28

    申请人： David R. Hembree ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  Salman Akram

    发明人： David R. Hembree ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  Salman Akram

    IPC分类号： G01R3102

    CPC分类号： G01R1/0483 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/48091 ,  H01L2224/81385 ,  H01L2924/01021 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/10155 ,  H01L2924/15311 ,  H01L2924/00014

    摘要： A semiconductor carrier and system for testing bumped semiconductor components, such as dice and packages, having contact bumps are provided. The carrier includes a base, an interconnect, and a force applying mechanism. The interconnect includes patterns of contact members adapted to electrically contact the contact bumps. The interconnect can include a substrate having contact members formed as recesses, or as projections, covered with conductive layers. Alternately, the interconnect can be a multi layered tape bonded directly to a base of the carrier. In addition to providing electrical connections, the contact members perform an alignment function by self centering the contact bumps within the contact members. The carrier can also include an alignment member configured to align the components with the interconnect. The system can include the carrier, a socket, and a testing apparatus such as a burn-in board in electrical communication with test circuitry.

    摘要翻译： 提供了一种半导体载体和系统，用于测试具有接触凸块的凸起的半导体部件，例如芯片和封装。 载体包括基底，互连和力施加机构。 互连包括适于电接触接触凸块的接触构件的图案。 互连可以包括具有形成为凹陷的接触构件的衬底，或者作为突出部的覆盖有导电层的衬底。 或者，互连可以是直接结合到载体的基底的多层带。 除了提供电连接之外，接触构件通过使接触构件内的接触凸块自对中来执行对准功能。 载体还可以包括配置成将部件与互连对准的对准部件。 该系统可以包括载体，插座和诸如与测试电路电连接的老化板的测试装置。