公开(公告)号：US20120199981A1

公开(公告)日：2012-08-09

申请号：US13364678

申请日：2012-02-02

Applicant: Se-young Jeong ,  Ho-geon Song ,  Ju-il Choi ,  Jae-hyun Phee

Inventor： Se-young Jeong ,  Ho-geon Song ,  Ju-il Choi ,  Jae-hyun Phee

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/10135 ,  H01L2224/11015 ,  H01L2224/11464 ,  H01L2224/11622 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13171 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/27436 ,  H01L2224/27622 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/81007 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/81862 ,  H01L2224/81986 ,  H01L2224/83862 ,  H01L2224/92143 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06575 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/3511 ,  H01L2924/3651 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device includes a first device including a first substrate and a first external connection terminal for connecting outside the first device; a second device stacked on the first device, the second device including a second substrate and a second external connection terminal for connecting outside the second device; an adhesive pattern disposed between the first device and second device, the adhesive pattern disposed in locations other than locations where the first external connection terminal and second external connection terminal are disposed, and the adhesive pattern causing the first device and second device, when stacked, to be spaced apart by a predetermined distance; and a plated layer disposed between and electrically and physically connecting the first external connection terminal and the second external connection terminal.

Abstract translation: 半导体器件包括：第一器件，包括第一衬底和用于连接第一器件外部的第一外部连接端子; 堆叠在第一装置上的第二装置，第二装置包括第二基板和用于连接第二装置外部的第二外部连接端子; 布置在第一装置和第二装置之间的粘合剂图案，布置在除了设置第一外部连接端子和第二外部连接端子的位置以外的位置的粘合剂图案以及当堆叠时引起第一装置和第二装置的粘合剂图案， 间隔开预定距离; 以及设置在电气和物理上连接第一外部连接端子和第二外部连接端子之间的镀层。

公开(公告)号：US08586477B2

公开(公告)日：2013-11-19

申请号：US13195128

申请日：2011-08-01

Applicant: Se-young Jeong ,  Ho-jin Lee ,  Ho-geon Song ,  Jae-hyun Phee

Inventor： Se-young Jeong ,  Ho-jin Lee ,  Ho-geon Song ,  Jae-hyun Phee

IPC: H01L21/44 ,  H01L21/00 ,  H01L23/04

CPC classification number: H01L21/76898 ,  H01L21/563 ,  H01L23/481 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03464 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2224/05609 ,  H01L2224/05613 ,  H01L2224/05614 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05649 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0567 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05683 ,  H01L2224/05684 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13171 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05552

Abstract: A semiconductor apparatus having a through electrode, a semiconductor package, and a method of manufacturing the semiconductor package are provided. The method of includes preparing a substrate including a buried via, the buried via having a first surface at a first end, and the buried via extending from a first substrate surface of the substrate into the substrate; planarizing a second substrate surface of the substrate opposite the first substrate surface to form a through via by exposing a second via surface at a second end of the buried via opposite the first end; forming a conductive capping layer on the exposed second via surface of the through via; and recessing the second substrate surface so that at least a first portion of the through via extends beyond the second substrate surface.

Abstract translation: 提供了具有贯通电极，半导体封装以及半导体封装的制造方法的半导体装置。 该方法包括制备包括掩埋通孔的衬底，所述埋入通孔在第一端具有第一表面，以及所述掩埋通孔从所述衬底的第一衬底表面延伸到所述衬底中; 平行化与第一衬底表面相对的衬底的第二衬底表面以通过在与第一端相对的埋置通孔的第二端处暴露第二通孔表面而形成通孔; 在通孔的暴露的第二通孔表面上形成导电覆盖层; 并且使所述第二衬底表面凹陷，使得所述通孔的至少第一部分延伸超出所述第二衬底表面。

公开(公告)号：US20120028412A1

公开(公告)日：2012-02-02

申请号：US13195128

申请日：2011-08-01

Applicant: Se-young Jeong ,  Ho-jin Lee ,  Ho-geon Song ,  Jae-hyun Phee

Inventor： Se-young Jeong ,  Ho-jin Lee ,  Ho-geon Song ,  Jae-hyun Phee

IPC: H01L21/50 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/563 ,  H01L23/481 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03464 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2224/05609 ,  H01L2224/05613 ,  H01L2224/05614 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05649 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0567 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05683 ,  H01L2224/05684 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13171 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05552

Abstract: A semiconductor apparatus having a through electrode, a semiconductor package, and a method of manufacturing the semiconductor package are provided. The method of includes preparing a substrate including a buried via, the buried via having a first surface at a first end, and the buried via extending from a first substrate surface of the substrate into the substrate; planarizing a second substrate surface of the substrate opposite the first substrate surface to form a through via by exposing a second via surface at a second end of the buried via opposite the first end; forming a conductive capping layer on the exposed second via surface of the through via; and recessing the second substrate surface so that at least a first portion of the through via extends beyond the second substrate surface.

Abstract translation: 提供了具有贯通电极，半导体封装以及半导体封装的制造方法的半导体装置。 该方法包括制备包括掩埋通孔的衬底，所述埋入通孔在第一端具有第一表面，以及所述掩埋通孔从所述衬底的第一衬底表面延伸到所述衬底中; 平行化与第一衬底表面相对的衬底的第二衬底表面以通过在与第一端相对的埋置通孔的第二端处暴露第二通孔表面而形成通孔; 在通孔的暴露的第二通孔表面上形成导电覆盖层; 并且使所述第二衬底表面凹陷，使得所述通孔的至少第一部分延伸超出所述第二衬底表面。

公开(公告)号：US20120282735A1

公开(公告)日：2012-11-08

申请号：US13439447

申请日：2012-04-04

Applicant: Jung-seok Ahn ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im ,  Chang-seong Jeon ,  Teak-hoon Lee ,  Sang-sick Park

Inventor： Jung-seok Ahn ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im ,  Chang-seong Jeon ,  Teak-hoon Lee ,  Sang-sick Park

IPC: H01L21/82

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11009 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/92125 ,  H01L2224/92143 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Abstract translation: 一种制造芯片堆叠的半导体封装的方法，该方法包括制备包括多个通过硅通孔（TSV）的多个第一芯片的基底晶片; 将包括多个第一芯片的基底晶片接合到支撑载体; 准备多个第二芯片; 通过将所述多个第二芯片接合到所述多个第一芯片来形成堆叠的芯片; 用密封部分密封堆叠的芯片; 并将堆叠的芯片彼此分离。

公开(公告)号：US08455301B2

公开(公告)日：2013-06-04

申请号：US13243493

申请日：2011-09-23

Applicant: Teak-hoon Lee ,  Won-keun Kim ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im

Inventor： Teak-hoon Lee ,  Won-keun Kim ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im

IPC: H01L21/00 ,  H01L29/06

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02372 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/1811 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of forming a semiconductor package includes attaching a semiconductor substrate on a support substrate, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region that separates respective ones of the semiconductor chips. A first cutting groove is formed that has a first kerf width between first and second ones of the plurality of first semiconductor chips. A plurality of second semiconductor chips is attached to the plurality of first semiconductor chips. A molding layer is formed so as to fill the first cutting groove and a second cutting groove having a second kerf width that is less than the first kerf width is formed in the molding layer so as to form individual molding layers covering one of the plurality of first semiconductor chips and one of the plurality of second semiconductor chips.

Abstract translation: 形成半导体封装的方法包括将半导体衬底附着在支撑衬底上，其中半导体衬底包括多个第一半导体芯片和分离各个半导体芯片的芯片切割区域。 形成第一切割槽，其具有在多个第一半导体芯片中的第一和第二半导体芯片之间的第一切口宽度。 多个第二半导体芯片附接到多个第一半导体芯片。 成型层形成为填充第一切割槽，并且在成型层中形成具有小于第一切口宽度的第二切口宽度的第二切割槽，以形成覆盖多个 第一半导体芯片和多个第二半导体芯片中的一个。

公开(公告)号：US08420450B2

公开(公告)日：2013-04-16

申请号：US13094216

申请日：2011-04-26

Applicant: Jun-young Ko ,  Jae-yong Park ,  Heui-seog Kim ,  Ho-geon Song

Inventor： Jun-young Ko ,  Jae-yong Park ,  Heui-seog Kim ,  Ho-geon Song

IPC: H01L21/16

CPC classification number: H01L21/52 ,  H01L21/56 ,  H01L21/565 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2225/06562

Abstract: A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding.

公开(公告)号：US20090278249A1

公开(公告)日：2009-11-12

申请号：US12458429

申请日：2009-07-13

Applicant: Ky-hyun Jung ,  Heui-seog Kim ,  Sang-jun Kim ,  Wha-su Sin ,  Ho-geon Song ,  Jun-young Ko

Inventor： Ky-hyun Jung ,  Heui-seog Kim ,  Sang-jun Kim ,  Wha-su Sin ,  Ho-geon Song ,  Jun-young Ko

IPC: H01L23/498 ,  H05K1/11 ,  H01B5/00

CPC classification number: H05K3/282 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/16503 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/243 ,  H05K3/3457 ,  H05K2201/0391 ,  H05K2201/0989 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A printed circuit board and method thereof and a solder ball land and method thereof. The example printed circuit board (PCB) may include a first solder ball land having a first surface treatment portion configured for a first type of resistance and a second solder ball land having a second surface treatment portion configured for a second type of resistance. The example solder ball land may include a first surface treatment portion configured for a first type of resistance and a second surface treatment portion configured for a second type of resistance. A first example method may include first treating a first surface of a first solder ball land to increase a first type of resistance and second treating a second surface of a second solder ball land to increase a second type of resistance other than the first type of resistance. A second example method may include first treating a solder ball land to increase a first type of resistance and second treating the solder ball land to increase a second type of resistance other than the first type of resistance.

Abstract translation: 一种印刷电路板及其方法和焊球地及其方法。 示例性印刷电路板（PCB）可以包括具有构造成用于第一类型电阻的第一表面处理部分的第一焊球焊盘和具有被配置为用于第二类型电阻的第二表面处理部分的第二焊球焊盘。 示例性焊球焊盘可以包括被配置为用于第一类型电阻的第一表面处理部分和被配置用于第二类型电阻的第二表面处理部分。 第一示例性方法可以包括首先处理第一焊球焊盘的第一表面以增加第一类型的电阻，并且第二处理第二焊球焊盘的第二表面以增加除第一类型电阻之外的第二类型的电阻 。 第二示例性方法可以包括首先处理焊球焊盘以增加第一类型的电阻，并且第二次处理焊球焊盘以增加除第一类型电阻之外的第二类型的电阻。

公开(公告)号：US07576438B2

公开(公告)日：2009-08-18

申请号：US11486064

申请日：2006-07-14

Applicant: Ky-hyun Jung ,  Heui-seog Kim ,  Sang-jun Kim ,  Wha-su Sin ,  Ho-geon Song ,  Jun-young Ko

Inventor： Ky-hyun Jung ,  Heui-seog Kim ,  Sang-jun Kim ,  Wha-su Sin ,  Ho-geon Song ,  Jun-young Ko

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K3/282 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/16503 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/243 ,  H05K3/3457 ,  H05K2201/0391 ,  H05K2201/0989 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A printed circuit board and method thereof and a solder ball land and method thereof. The example printed circuit board (PCB) may include a first solder ball land having a first surface treatment portion configured for a first type of resistance and a second solder ball land having a second surface treatment portion configured for a second type of resistance. The example solder ball land may include a first surface treatment portion configured for a first type of resistance and a second surface treatment portion configured for a second type of resistance. A first example method may include first treating a first surface of a first solder ball land to increase a first type of resistance and second treating a second surface of a second solder ball land to increase a second type of resistance other than the first type of resistance. A second example method may include first treating a solder ball land to increase a first type of resistance and second treating the solder ball land to increase a second type of resistance other than the first type of resistance.

公开(公告)号：US08637969B2

公开(公告)日：2014-01-28

申请号：US13908728

申请日：2013-06-03

Applicant: Teak-hoon Lee ,  Won-keun Kim ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im

Inventor： Teak-hoon Lee ,  Won-keun Kim ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im

IPC: H01L23/02 ,  H01L21/00

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02372 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/1811 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of forming a semiconductor package having a large capacity and a reduced or minimized volume includes: attaching a semiconductor substrate on a support substrate using an adhesive layer, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region, wherein first and second ones of the plurality of first semiconductor chips are separated each other by the chip cutting region, and the semiconductor substrate includes a first surface on which an active area is formed and a second surface opposite to the first surface; forming a first cutting groove having a first kerf width, between the first and second ones of the plurality of first semiconductor chips, so that the semiconductor substrate is separated into a plurality of first semiconductor chips; attaching a plurality of second semiconductor chips corresponding to the first semiconductor chips, respectively, to the plurality of first semiconductor chips; forming a molding layer so as to fill the first cutting groove; and forming a second cutting groove having a second kerf width that is less than the first kerf width, in the molding layer, so as to separate the molding layer into individual molding layers covering one of the plurality of first semiconductor chips and corresponding one of the plurality of second semiconductor chips.

Abstract translation: 一种形成具有大容量和减小或最小化体积的半导体封装的方法包括：使用粘合剂层将半导体衬底附着在支撑衬底上，其中半导体衬底包括多个第一半导体芯片和切屑区域，其中 多个第一半导体芯片中的第一和第二半导体芯片通过芯片切割区域彼此分离，并且半导体衬底包括其上形成有源区域的第一表面和与第一表面相对的第二表面; 在所述多个第一半导体芯片中的第一和第二半导体芯片之间形成具有第一切口宽度的第一切割槽，使得半导体基板被分离成多个第一半导体芯片; 分别将对应于第一半导体芯片的多个第二半导体芯片附着到多个第一半导体芯片; 形成模塑层以填充第一切割槽; 以及在成形层中形成具有小于第一切口宽度的第二切口宽度的第二切割槽，以将模制层分离成覆盖多个第一半导体芯片中的一个的各个成型层和相应的一个 多个第二半导体芯片。

公开(公告)号：US08637350B2

公开(公告)日：2014-01-28

申请号：US13439447

申请日：2012-04-04

Applicant: Jung-seok Ahn ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im ,  Chang-seong Jeon ,  Teak-hoon Lee ,  Sang-sick Park

Inventor： Jung-seok Ahn ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im ,  Chang-seong Jeon ,  Teak-hoon Lee ,  Sang-sick Park

IPC: H01L21/00

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11009 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/92125 ,  H01L2224/92143 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Abstract translation: 一种制造芯片堆叠的半导体封装的方法，所述方法包括制备包括多个第一芯片的基片，每个第一芯片均具有穿硅通孔（TSV）; 将包括多个第一芯片的基底晶片接合到支撑载体; 准备多个第二芯片; 通过将所述多个第二芯片接合到所述多个第一芯片来形成堆叠的芯片; 用密封部分密封堆叠的芯片; 并将堆叠的芯片彼此分离。