公开(公告)号：US09559447B2

公开(公告)日：2017-01-31

申请号：US15062136

申请日：2016-03-06

申请人： HSIO Technologies, LLC

发明人： James J. Rathburn

IPC分类号： H01R43/20 ,  H01R12/70 ,  H01R13/405 ,  H05K3/34

CPC分类号： H01R12/7076 ,  H01R12/7082 ,  H01R13/405 ,  H01R43/205 ,  H05K3/3436 ,  H05K2201/10325 ,  Y02P70/613

摘要： An electrical connector and a method of make the same. The electrical connector includes an insulator housing formed with a plurality of through holes extending from a first surface to a second surface of the insulator housing. A flowable polymeric material is located adjacent at least one retention region in each of the through holes. Contact members are positioned within each of the through holes. Energy and/or pressure is applied to the electrical connector so the flowable polymeric material flows into engagement with retention features on the contact members. The electrical connector is cooled so the flowable polymeric material fuses to the contact members in a retention regions.

摘要翻译： 电连接器及其制造方法。 电连接器包括形成有从绝缘体外壳的第一表面延伸到第二表面的多个通孔的绝缘体外壳。 可流动的聚合材料位于每个通孔中的至少一个保持区域附近。 接触构件位于每个通孔内。 能量和/或压力被施加到电连接器，使得可流动的聚合物材料流入与接触构件上的保留特征的接合。 电连接器被冷却，使得可流动的聚合材料在保持区域中熔化到接触构件。

公开(公告)号：US09350093B2

公开(公告)日：2016-05-24

申请号：US14271801

申请日：2014-05-07

申请人： HSIO TECHNOLOGIES, LLC

发明人： Jim Rathburn

IPC分类号： H01R12/57 ,  H01R43/16 ,  H01R12/52 ,  H05K1/02 ,  H05K1/14 ,  H01R12/71 ,  H01R13/24 ,  H05K1/16 ,  H05K3/40

CPC分类号： H01R12/57 ,  H01L2224/16225 ,  H01R12/52 ,  H01R12/523 ,  H01R12/714 ,  H01R13/2421 ,  H01R43/16 ,  H05K1/023 ,  H05K1/141 ,  H05K1/16 ,  H05K3/4007 ,  H05K2201/10378 ,  Y10T29/49204

摘要： A electrical interconnect adapted to provide an interface between contact pads on an IC device and a PCB, including a multi-layered substrate with a first surface with a plurality of first openings having first cross-sections, a second surface with a plurality of second openings having second cross-sections, and center openings connecting the first and second openings. The contact members include first contact tips extending through the first opening and above the first surface, second contact tips extending through the second openings and above the second surface, and center portions located in the center openings. The center portions include a shape adapted to bias the first and second contact tips toward the IC device and PCB, respectively. A dielectric material different from the material of the substrate is located in at least one of the first opening, the second opening, or the center opening.

摘要翻译： 一种适于提供在IC器件上的接触焊盘与PCB之间的接口的电互连，包括具有第一表面的多层基底，多个第一开口具有第一横截面，第二表面具有多个第二开口 具有第二横截面和连接第一和第二开口的中心开口。 接触构件包括延伸穿过第一开口并在第一表面上方的第一接触尖端，延伸穿过第二开口并在第二表面上方的第二接触末端以及位于中心开口中的中心部分。 中心部分包​​括适于分别朝向IC器件和PCB偏置第一和第二接触尖端的形状。 与基板的材料不同的介电材料位于第一开口，第二开口或中心开口中的至少一个中。

公开(公告)号：US09320133B2

公开(公告)日：2016-04-19

申请号：US13880461

申请日：2011-12-05

申请人： James Rathburn

发明人： James Rathburn

IPC分类号： H05K1/02 ,  H01R43/02 ,  H05K3/40 ,  H05K1/14 ,  H05K3/34

CPC分类号： H05K1/0228 ,  H01R43/0256 ,  H05K1/0296 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/40 ,  H05K3/4046 ,  H05K2201/10378 ,  H05K2203/041 ,  Y10T29/49147

摘要： A surface mount electrical interconnect is disclosed that provides an interface between a PCB and solder balls of a BGA device. The electrical interconnect includes a socket substrate and a plurality of electrically conductive contact members. The socket substrate has a first layer with a plurality of openings configured to receive solder balls of the BGA device and has a second layer with a plurality of slots defined therethrough that correspond to the plurality of openings. The contact members may be disposed in the openings in the first layer and through the plurality of slots of the second layer of the socket substrate. The contact members can be configured to engage a top portion, a center diameter, and a lower portion of the solder ball of the BGA device. Each contact member electrically couples a solder ball on the BGA device to the PCB.

摘要翻译： 公开了一种表面贴装电互连，其提供了PCB与BGA器件的焊球之间的界面。 电互连包括插座衬底和多个导电接触构件。 插座衬底具有第一层，其具有多个开口，其被配置为接收BGA器件的焊球，并且具有第二层，其中限定了多个槽，其对应于多个开口。 接触构件可以设置在第一层中的开口中并且穿过插座衬底的第二层的多个槽中。 接触构件可以构造成接合BGA装置的焊球的顶部，中心直径和下部。 每个接触构件将BGA器件上的焊球电耦合到PCB。

公开(公告)号：US09232654B2

公开(公告)日：2016-01-05

申请号：US13879783

申请日：2011-10-18

申请人： James Rathburn

发明人： James Rathburn

IPC分类号： H05K1/00 ,  H05K1/18 ,  H01L23/538 ,  H05K3/32 ,  H05K3/40 ,  H05K3/46 ,  H05K1/11 ,  H05K1/16 ,  H05K3/12 ,  H05K3/30 ,  H01L23/498 ,  H05K1/02

CPC分类号： H05K1/18 ,  H01L23/49811 ,  H01L23/5383 ,  H01L2224/16 ,  H01L2924/09701 ,  H01L2924/12044 ,  H05K1/0274 ,  H05K1/111 ,  H05K1/115 ,  H05K1/16 ,  H05K3/1291 ,  H05K3/30 ,  H05K3/325 ,  H05K3/4007 ,  H05K3/4664 ,  H05K2201/0133 ,  Y10T29/49155

摘要： A high performance electrical interconnect adapted to provide an interface between terminals on first and second circuit members. The electrical interconnect includes a first circuitry layer with a first surface and a second surface having a plurality of contact pads adapted to electrically coupled with the terminals on the first circuit member. At least one dielectric layer is printed on the first surface of the first circuitry layer. The dielectric layer includes a plurality recesses. A conductive material is deposited in at least a portion of the recesses to create circuit geometry electrically coupled with the first circuitry layer. A second circuitry layer includes a first surface a plurality of contact pads adapted to electrically couple with the terminals on the second circuit member and a second surface attached to the dielectric layers. The circuit geometry electrically couples the first circuitry layer to the second circuitry layer.

摘要翻译： 一种适用于在第一和第二电路构件上的端子之间提供接口的高性能电互连。 电互连包括具有第一表面的第一电路层和具有适于与第一电路构件上的端子电耦合的多个接触焊盘的第二表面。 至少一个电介质层被印刷在第一电路层的第一表面上。 电介质层包括多个凹部。 导电材料沉积在凹陷的至少一部分中以产生与第一电路层电耦合的电路几何形状。 第二电路层包括第一表面，多个接触焊盘，其适于与第二电路部件上的端子电耦合，以及附接到电介质层的第二表面。 电路几何电耦合第一电路层到第二电路层。

公开(公告)号：US09136196B2

公开(公告)日：2015-09-15

申请号：US13318200

申请日：2010-05-27

申请人： James Rathburn

发明人： James Rathburn

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L21/683 ,  H01L25/065 ,  H01L23/525 ,  H01L23/00

CPC分类号： H01L23/3114 ,  H01L21/6836 ,  H01L23/525 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/20 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68372 ,  H01L2224/02335 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/20 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/05552

摘要： A wafer-level package for semiconductor devices and a method for making the package. At least one dielectric layer is selectively printed on at least a portion of the semiconductor devices creating first recesses aligned with a plurality of electrical terminals on the semiconductor devices. A conductive material is printed in the first recesses to form contact members on the semiconductor devices. At least one dielectric layer is selectively printed to create a plurality of second recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the second recesses to create a circuit geometry. The circuit geometry includes a plurality of exposed terminals adapted to electrically couple to another circuit member. The wafer is diced to provide a plurality of discrete packaged semiconductor devices.

摘要翻译： 一种用于半导体器件的晶片级封装以及一种制造封装的方法。 至少一个电介质层被选择性地印刷在半导体器件的至少一部分上，形成与半导体器件上的多个电端子对准的第一凹槽。 在第一凹部中印刷导电材料，以在半导体器件上形成接触部件。 选择性地印刷至少一个电介质层以产生对应于目标电路几何形状的多个第二凹部。 导电材料印刷在第二凹槽的至少一部分中以产生电路几何形状。 电路几何形状包括适于电耦合到另一电路部件的多个暴露端子。 切割晶片以提供多个分立的封装半导体器件。

公开(公告)号：US08984748B2

公开(公告)日：2015-03-24

申请号：US13319228

申请日：2010-06-28

申请人： James Rathburn

发明人： James Rathburn

IPC分类号： H05K3/32 ,  G01R3/00 ,  G01R1/04 ,  G01R1/073

CPC分类号： G01R3/00 ,  G01R1/0491 ,  G01R1/0735 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49204 ,  Y10T29/49222

摘要： A socket assembly that forms a solderless electrical interconnection between terminals on a singulated integrated circuit device and another circuit member. The socket housing has an opening adapted to receive the singulated integrated circuit device. The compliant printed circuit is positioned relative to the socket housing to electrically couple with the terminals on a singulated integrated circuit device located in the opening. The compliant printed circuit includes a dielectric base layer printed onto a surface of a fixture, while leaving cavities in the surface of the fixture exposed. A plurality of contact members are formed in the plurality of cavities in the fixture and coupled to the dielectric base layer. The contact members are exposed wherein the compliant printed circuit is removed from the fixture. At least one dielectric layer with recesses corresponding to a target circuit geometry is printed on the dielectric base layer. A conductive material is deposited in at least a portion of the recesses to form conductive traces electrically coupling the contact members to the other circuit member.

摘要翻译： 插座组件，其在单个集成电路器件和另一个电路部件之间形成端子之间的无焊接电气互连。 插座壳体具有适于容纳单个集成电路装置的开口。 顺应印刷电路相对于插座壳体定位，以在位于开口中的单个集成电路装置上与端子电耦合。 柔性印刷电路包括印刷在固定装置表面上的电介质基层，同时在固定装置表面露出空腔。 多个接触构件形成在固定装置中的多个空腔中，并与电介质基底层耦合。 接触构件被暴露，其中柔性印刷电路从固定装置移除。 具有对应于目标电路几何形状的凹部的至少一个电介质层被印刷在电介质基底层上。 导电材料沉积在凹陷的至少一部分中以形成将接触构件电耦合到另一个电路构件的导电迹线。

公开(公告)号：US08981568B2

公开(公告)日：2015-03-17

申请号：US13319120

申请日：2010-06-07

申请人： James Rathburn

发明人： James Rathburn

IPC分类号： H01L23/48 ,  H01L23/00 ,  B23K1/00 ,  B23K20/00 ,  H01L21/683 ,  H01L23/552 ,  H01L25/065 ,  H01L23/31

CPC分类号： H01L24/50 ,  B23K1/0016 ,  B23K20/004 ,  B23K2101/42 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/48 ,  H01L23/552 ,  H01L24/86 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2223/6677 ,  H01L2225/06524 ,  H01L2225/06568 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package with simulated wirebonds. A substrate is provided with a plurality of first pads on a first surface and a plurality of second pads on a second surface. Each of the first pads are electrically coupled to one or more of the second pads. At least one semiconductor device is located proximate the first surface of a substrate. The simulated wirebonds include at least a first dielectric layer selectively printed to create a plurality of recesses, and a conductive material located in the recesses to form first and second contact pads, and electrical traces electrically coupling the first and second contact pads. The first contact pads are electrically coupled to terminals on the semiconductor device and the second contact pads are electrically coupled to the first pads on the first surface of the substrate. An overmolding material seals the semiconductor device and the simulated wirebonds.

摘要翻译： 具有模拟线束的半导体封装。 衬底在第一表面上设置有多个第一焊盘，在第二表面上设置有多个第二焊盘。 每个第一焊盘电耦合到一个或多个第二焊盘。 至少一个半导体器件位于衬底的第一表面附近。 模拟线圈包括至少第一电介质层，其选择性地印刷以产生多个凹陷，以及位于凹部中以形成第一和第二接触焊盘的导电材料以及电耦合第一和第二接触焊盘的电迹线。 第一接触焊盘电耦合到半导体器件上的端子，并且第二接触焊盘电耦合到衬底的第一表面上的第一焊盘。 包覆成型材料密封半导体器件和模拟引线。

公开(公告)号：US20150013901A1

公开(公告)日：2015-01-15

申请号：US14327916

申请日：2014-07-10

申请人： HSIO TECHNOLOGIES, LLC

发明人： JAMES RATHBURN

IPC分类号： H05K3/46 ,  H05K3/12 ,  H01L21/768 ,  H05K3/18

CPC分类号： H01L21/76877 ,  B33Y80/00 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K1/0393 ,  H05K1/16 ,  H05K3/0005 ,  H05K3/4069 ,  H05K3/421 ,  H05K3/429 ,  H05K3/465 ,  H05K3/4658 ,  H05K2201/09272 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/098 ,  H05K2203/013 ,  H05K2203/1476 ,  H01L2924/00014

摘要： A system and method for “pixelating” a three-dimensional circuit structure into a three-dimensional matrix of cubes that are located with respect to a coordinate system. The design step is typically performed on a conventional computer using computer aided design software that pixelates the proposed circuit structure into an array of uniformly sized cube. The fabrication process involves adding and subtracting bulk materials from the individual cubic positions within the pixelated representation of the circuit structure. Various existing and new techniques can be used to add or subtract bulk materials as the cubic positions within the matrix to construct the circuit structure.

摘要翻译： 将三维电路结构“像素化”为相对于坐标系定位的三维矩阵的三维矩阵的系统和方法。 设计步骤通常在使用计算机辅助设计软件的常规计算机上执行，将所提出的电路结构像素化为均匀尺寸的立方体的阵列。 制造过程包括在电路结构的像素化表示内从各个立方体位置添加和减去大量材料。 可以使用各种现有技术和新技术将体积材料作为立方体位置加入或减去以构成电路结构。

公开(公告)号：US08704377B2

公开(公告)日：2014-04-22

申请号：US13969953

申请日：2013-08-19

申请人： HSIO Technologies, LLC

发明人： James Rathburn

IPC分类号： H01L23/48

CPC分类号： H01L23/48 ,  B82Y10/00 ,  H01R23/722 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/141 ,  H05K3/32 ,  H05K3/3436 ,  H05K3/4038 ,  H05K3/4069 ,  H05K7/1069 ,  H05K7/1092 ,  H05K2201/049 ,  Y10T29/4913 ,  Y10T29/49147

摘要： An electrical interconnect providing an interconnect between contacts on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a resilient substrate with a plurality of through holes extending from a first surface to a second surface. A resilient material is located in the through holes. The resilient material includes an opening extending from the first surface to the second surface. A plurality of discrete, free-flowing conductive nano-particles are located in the openings of the resilient material. The conductive particles are substantially free of non-conductive materials. A plurality of first contact members are located in the through holes adjacent the first surface and a plurality of second contact members are located in the through holes adjacent the second surface. The first and second contact members are electrically coupled to the nano-particles.

摘要翻译： 提供IC器件上的触点与印刷电路板（PCB）上的接触焊盘之间的互连的电互连。 电互连包括具有从第一表面延伸到第二表面的多个通孔的弹性基底。 弹性材料位于通孔中。 弹性材料包括从第一表面延伸到第二表面的开口。 多个离散的自由流动的导电纳米颗粒位于弹性材料的开口中。 导电颗粒基本上不含非导电材料。 多个第一接触构件位于邻近第一表面的通孔中，并且多个第二接触构件位于与第二表面相邻的通孔中。 第一和第二接触构件电耦合到纳米颗粒。

公开(公告)号：US08525346B2

公开(公告)日：2013-09-03

申请号：US13448914

申请日：2012-04-17

申请人： James Rathburn

发明人： James Rathburn

IPC分类号： H01L23/48

CPC分类号： H01L23/48 ,  B82Y10/00 ,  H01R23/722 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/141 ,  H05K3/32 ,  H05K3/3436 ,  H05K3/4038 ,  H05K3/4069 ,  H05K7/1069 ,  H05K7/1092 ,  H05K2201/049 ,  Y10T29/4913 ,  Y10T29/49147

摘要： An electrical interconnect providing an interconnect between contacts on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a substrate with a plurality of through holes extending from a first surface to a second surface. A resilient material is located in the through holes. The resilient material includes an opening extending from the first surface to the second surface. A plurality of discrete, free-flowing conductive nano-particles are located in the openings of the resilient material. The conductive particles are substantially free of non-conductive materials. A plurality of first contact members are located in the through holes adjacent the first surface and a plurality of second contact members are located in the through holes adjacent the second surface. The first and second contact members are electrically coupled to the nano-particles.

摘要翻译： 提供IC器件上的触点与印刷电路板（PCB）上的接触焊盘之间的互连的电互连。 电互连包括具有从第一表面延伸到第二表面的多个通孔的基底。 弹性材料位于通孔中。 弹性材料包括从第一表面延伸到第二表面的开口。 多个离散的自由流动的导电纳米颗粒位于弹性材料的开口中。 导电颗粒基本上不含非导电材料。 多个第一接触构件位于邻近第一表面的通孔中，并且多个第二接触构件位于与第二表面相邻的通孔中。 第一和第二接触构件电耦合到纳米颗粒。