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    MONOLITHIC WAFER HAVING INTERCONNECTION SYSTEM INCLUDING PROGRAMMABLE INTERCONNECTION LAYER
    54.
    发明申请
    MONOLITHIC WAFER HAVING INTERCONNECTION SYSTEM INCLUDING PROGRAMMABLE INTERCONNECTION LAYER 审中-公开
    具有互连系统的单片式波形，包括可编程互连层

    公开(公告)号：WO1985003805A1

    公开(公告)日：1985-08-29

    申请号：PCT/US1985000281

    申请日：1985-02-21

    Applicant: MOSAIC SYSTEMS, INC. ,  STOPPER, Herbert ,  PERKINS, Cornelius, Churchill

    Inventor： MOSAIC SYSTEMS, INC.

    IPC: H01L23/48

    CPC classification number: H01L23/5383 ,  H01L23/5382 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/49175 ,  H01L2924/10253 ,  H01L2924/15184 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00014

    Abstract: Wafer substrate for intergrated circuits (1) which by itself may be made either of conductive or non-conductive material. This substrate carries two planes or layers of patterned metal (19, 20) thus providing two principal levels of interconnection. A programmable amorphous silicon insulation layer (21) is placed between the metal layers. There are sheet lower metal layers with an insulator which permit power distribution across the wafer. Connections between the metal layers or between the metal layer and the substrate can be made through via holes in the insulator layers or layers, respectively. Pedestals are provided for bonding. Systems can be formed by interconnection discrete die formed on the wafer or by connection thereto, with hybrid circuits being disclosed. The method of manufacture of the wafer, a capacitive device and an antifuse are disclosed.

    Abstract translation: 用于集成电路（1）的晶片衬底本身可以由导电材料或非导电材料制成。 该衬底承载两层图案化的金属（19,20），从而提供两个主要的互连级别。 可编程非晶硅绝缘层（21）放置在金属层之间。 存在具有绝缘体的片状下金属层，其允许跨晶片的功率分配。 金属层之间或金属层与基板之间的连接可分别通过绝缘体层或层中的通孔形成。 提供基座用于接合。 系统可以通过形成在晶片上的互连离散芯片或通过与其连接而形成，其中公开了混合电路。 公开了晶片，电容器件和反熔丝的制造方法。

    ENHANCED PACKAGE THERMAL MANAGEMENT USING EXTERNAL AND INTERNAL CAPACITIVE THERMAL MATERIAL
    55.
    发明申请
    ENHANCED PACKAGE THERMAL MANAGEMENT USING EXTERNAL AND INTERNAL CAPACITIVE THERMAL MATERIAL 审中-公开
    使用外部和内部电容热材料的增强型封装热管理

    公开(公告)号：WO2013158721A1

    公开(公告)日：2013-10-24

    申请号：PCT/US2013/036907

    申请日：2013-04-17

    Applicant: QUALCOMM INCORPORATED

    Inventor： CHIRIAC, Victor A. ,  LISK, Durodami J. ,  RADOJCIC, Ratibor

    IPC: H01L23/42 ,  H01L23/433

    CPC classification number: H01L23/4275 ,  H01L23/4334 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311

    Abstract: An apparatus has external and/or internal capacitive thermal material for enhanced thermal package management. The apparatus includes an integrated circuit (IC) package having a heat generating device. The apparatus also includes a heat spreader having a first side that is attached to the IC package. The apparatus also includes capacitive thermal material reservoirs contacting the first side of the heat spreader. The capacitive thermal material reservoirs may be disposed laterally relative to the heat generating device.

    Abstract translation: 一种具有用于增强热封装管理的外部和/或内部电容热材料的装置。 该装置包括具有发热装置的集成电路（IC）封装。 该装置还包括具有附接到IC封装的第一侧的散热器。 该装置还包括接触散热器第一侧的电容式热材料储存器。 电容热材料储存器可以相对于发热装置横向设置。

    DEVICES AND METHODS RELATED TO A BARRIER FOR METALLIZATION IN HETEROJUNCTION BIPOLAR TRANSISTOR PROCESSES
    56.
    发明申请
    DEVICES AND METHODS RELATED TO A BARRIER FOR METALLIZATION IN HETEROJUNCTION BIPOLAR TRANSISTOR PROCESSES 审中-公开
    用于异相双极晶体管工艺中金属化的阻挡层的装置和方法

    公开(公告)号：WO2013074680A1

    公开(公告)日：2013-05-23

    申请号：PCT/US2012/065090

    申请日：2012-11-14

    Applicant: SKYWORKS SOLUTIONS, INC.

    Inventor： CISMARU, Cristian ,  ZAMPARDI, Peter, J., Jr.

    IPC: H01L29/73 ,  H04B1/00 ,  G01R31/26

    CPC classification number: H01L27/0658 ,  H01L21/8252 ,  H01L22/14 ,  H01L27/0605 ,  H01L28/60 ,  H01L29/0692 ,  H01L29/205 ,  H01L29/41708 ,  H01L29/66242 ,  H01L29/737 ,  H01L29/7371 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/15184 ,  H01L2924/15192 ,  H04M1/026 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: Disclosed are structures and methods related to a barrier layer for metallization of a selected semiconductor such as indium gallium phosphide (InGaP). In some embodiments, the barrier layer can include tantalum nitride (TaN). Such a barrier layer can provide desirable features such as barrier functionality, improved adhesion of a metal layer, reduced diffusion, reduced reactivity between the metal and InGaP, and stability during the fabrication process. In some embodiments, structures formed in such a manner can be configured as an emitter of a gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) or an on-die high-value capacitance element. In some embodiments, some of the foregoing structures can be configured as a capacitance element having a capacitance value representative of the thickness of the emitter layer. Accordingly, monitoring of such a capacitance value during various HBT processes allows monitoring of the integrity of the emitter layer.

    Abstract translation: 公开了与用于诸如铟镓磷化物（InGaP）的选定半导体的金属化的阻挡层有关的结构和方法。 在一些实施例中，阻挡层可以包括氮化钽（TaN）。 这种阻挡层可以提供期望的特征，例如屏障功能，金属层的改善的粘附，减小的扩散，金属和InGaP之间的反应性降低，以及制造过程中的稳定性。 在一些实施例中，以这种方式形成的结构可被配置为砷化镓（GaAs）异质结双极晶体管（HBT）的发射极或片上高电容元件。 在一些实施例中，前述结构中的一些可被配置为具有代表发射极层的厚度的电容值的电容元件。 因此，在各种HBT过程中监测这种电容值允许监测发射极层的完整性。

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