Abstract:
A microelectronic assembly can include a microelectronic device (310) having device contacts (312) exposed at a surface (328) thereof and an interconnection element having element contacts (340) and having a face adjacent to the microelectronic device. Conductive elements (365), e.g., wirebonds connect the device contacts with the element contacts and have portions extending in runs above the surface of the microelectronic device. A conductive layer (360) has a conductive surface (375) disposed at at least a substantially uniform distance above or below the plurality of the runs of the conductive elements. In some cases, the conductive material (360) can have first and second dimensions (326, 336) in first and second horizontal directions which are smaller than first and second corresponding dimensions (324, 334) of the microelectronic device. The conductive material (360) is connectable to a source of reference potential so as to achieve a desired impedance for the conductive elements.
Abstract:
A microelectronic assembly can include a microelectronic device, e.g., semiconductor chip (910), connected together with an interconnection element (930), e.g., substrate, the latter having signal contacts (990) and reference contacts (980). The reference contacts can be connectable to a source of reference potential such as ground or a voltage source other than ground such as a voltage source used for power. Signal conductors, e.g., signal wirebonds (965) can be connected to device contacts (912) exposed at a surface of the microelectronic device (910). Reference conductors, e.g., reference wirebonds (975) can be provided, at least one of which can be connected with two reference contacts (980) of the interconnection element (930). The reference wirebond (975) can have a run which extends at an at least substantially uniform spacing from a signal conductor, e.g., signal wirebond (965) that is connected to the microelectronic device over at least a substantial portion of the length of the signal conductor. In such manner a desired impedance may be achieved for the signal conductor.
Abstract:
A microelectronic assembly 100 is provided which includes a first element 110 consisting essentially of at least one of semiconductor or inorganic dielectric material having a surface 103 facing and attached to a major surface 104 of a microelectronic element 102 at which a plurality of conductive pads 106 are exposed, the microelectronic element 102 having active semiconductor devices therein. A first opening 111 extends from an exposed surface 118 of the first element 110 towards the surface 103 attached to the microelectronic element 102, and a second opening 113 extends from the first opening 111 to a first one of the conductive pads 106, wherein where the first and second openings meet, interior surfaces 121, 123 of the first and second openings extend at different angles relative to the major surface 104 of the microelectronic element 102. A conductive element 114 extends within the first and second openings 111, 113 and contacts the at least one conductive pad 106.
Abstract:
A stacked microelectronic assembly is provided which includes first and second stacked microelectronic elements (101, 102). Each of the first and second microelectronic elements can include a conductive layer (610) extending along a face (608) of such microelectronic element. At least one of the first and second microelectronic elements can include a recess (618) extending from the rear surface towards the front surface, and a conductive via (605) extending from the recess through the bond pad (603) and electrically connected to the bond pad, with a conductive layer (610) connected to the via and extending along a rear face (608) of the microelectronic element (101, 102) towards an edge (620) of the microelectronic element. A plurality of leads (224) can extend from the conductive layers (610) of the first and second microelectronic elements and a plurality of terminals (616) of the assembly can be electrically connected with the leads.
Abstract:
A microelectronic package (20) includes a microelectronic element (22) having faces and contacts (26), a flexible substrate (30) overlying and spaced from a first face (24) of the microelectronic element (22), and a plurality of conductive terminals (42) exposed at a surface of the flexible substrate. The conductive terminals (42) are electrically interconnected with the microelectronic element (22) and the flexible substrate (30) includes a gap (50) extending at least partially around at least one of the conductive terminals (42). In certain embodiments, the package includes a support layer, such as a compliant layer (48), disposed between the first face (24) of the microelectronic element (22) and the flexible substrate (30). In other embodiments, the support layer includes at least one opening that is at least partially aligned with one of the conductive terminals.
Abstract:
A microelectronic assembly includes a microelectronic element (20), such as a semiconductor wafer or semiconductor chip, having a first surface (22) and contacts (24) accessible at the first surface (22), and a compliant layer (26) overlying the first surface of the microelectronic element, the compliant layer (26) having openings in substantial alignment with the contacts (24) of the microelectronic element. The assembly desirably includes conductive posts (38) overlying the compliant layer (26) and projecting away from the first surface (22) of the microelectronic element (20), the conductive posts (38) being electrically interconnected with the contacts (24) of the microelectronic element (20) by elongated, electrically conductive elements extending between the contacts (24) and the conductive posts (38).
Abstract:
A method of making a microelectronic assembly includes providing a microelectronic package having a substrate 400, a microelectronic element 410 overlying the substrate 400 and at least two conductive elements 418 projecting from a surface 402 of the substrate 400, the at least two conductive elements 418 having surfaces 434 remote from the surface 402 of the substrate 400. The method includes compressing the at least two conductive elements 418 so that the remote surfaces 434 thereof lie in a common plane, and after the compressing step, providing an encapsulant material 430 around the at least two conductive elements 418 for supporting the microelectronic package and so that the remote surfaces 434 of the at least two conductive elements 418 remain accessible at an exterior surface of the encapsulant material 430.
Abstract:
As disclosed herein, structures and methods are provided for forming capped chips. As provided by the disclosed method, a metal base pattern (26) is formed on a chip (8) insulated from wiring (11) of the chip, and a cap (42) is formed including a metal. The cap (42) is joined to the metal base pattern (26) on the chip to form the capped chip (48). In one embodiment, a front surface (9) of the chip is exposed which extends from a contact (14) or (16) of the chip to an edge (13) of the chip (8). In another embodiment, a conductive connection is formed to the contact (14) or (16), the conductive connection extending from the contact to a terminal (46) at an exposed plane (49) above the front surface (9) of the chip (8).
Abstract:
Various embodiments of packaged chips and ways of fabricating them are disclosed herein. One such packaged chip disclosed herein includes a chip having a front face, a rear face opposite the front face, and a device at one of the front and rear faces, the device being operable as transducer of at least one of acoustic energy and electromagnetic energy, and the chip including a plurality of bond pads exposed to one of the front and rear faces. The packaged chip includes a package element having a dielectric element and a metal layer disposed on the dielectric element, the package element having an inner surface facing the chop and an outer surface facing away from the chip. The metal layer includes a plurality of contacts exposed at at least one of the inner and outer surfaces, the contacts conductively connected to the bond pads. The metal layer further includes a first opening for passage of the at least one of acoustic energy and electromagnetic energy in a direction of at least one of the said device and from said device.
Abstract:
A method of fabricating a semiconductor assembly 10 can include providing a semiconductor element 20 having a front surface 21, a rear surface 22, and a plurality of conductive pads 50, forming at least one hole 40 extending at least through a respective one of the conductive pads 50 by processing applied to the respective conductive pad 50 from above the front surface 21, forming an opening 30 extending from the rear surface 22 at least partially through a thickness of the semiconductor element 20, such that the at least one hole 30 and the opening 40 meet at a location between the front and rear surfaces, and forming at least one conductive element 60, 80 exposed at the rear surface 22 for electrical connection to an external device, the at least one conductive element extending within the at least one hole 30 and at least into the opening 40, the conductive element being electrically connected with the respective conductive pad 50.