STACKED MICROELECTRONIC ASSEMBLY WITH MICROELECTRONIC ELEMENTS HAVING VIAS EXTENDING THROUGH BOND PADS
    2.
    发明申请
    STACKED MICROELECTRONIC ASSEMBLY WITH MICROELECTRONIC ELEMENTS HAVING VIAS EXTENDING THROUGH BOND PADS 审中-公开
    具有通过粘结垫延伸的VIAS的微电子元件的堆叠微电子组件

    公开(公告)号:WO2010104610A8

    公开(公告)日:2011-11-17

    申请号:PCT/US2010000777

    申请日:2010-03-12

    Abstract: A stacked microelectronic assembly is provided which includes first and second stacked microelectronic elements (101, 102). Each of the first and second microelectronic elements can include a conductive layer (610) extending along a face (608) of such microelectronic element. At least one of the first and second microelectronic elements can include a recess (618) extending from the rear surface towards the front surface, and a conductive via (605) extending from the recess through the bond pad (603) and electrically connected to the bond pad, with a conductive layer (610) connected to the via and extending along a rear face (608) of the microelectronic element (101, 102) towards an edge (620) of the microelectronic element. A plurality of leads (224) can extend from the conductive layers (610) of the first and second microelectronic elements and a plurality of terminals (616) of the assembly can be electrically connected with the leads.

    Abstract translation: 提供堆叠的微电子组件,其包括第一和第二堆叠的微电子元件(101,102)。 第一和第二微电子元件中的每一个可以包括沿着这种微电子元件的面(608)延伸的导电层(610)。 第一和第二微电子元件中的至少一个可以包括从后表面朝向前表面延伸的凹槽(618),以及从凹部穿过接合焊盘(603)延伸并电连接到 接合焊盘,其中导电层(610)连接到通孔并且沿着微电子元件(101,102)的后表面(608)朝着微电子元件的边缘(620)延伸。 多个引线(224)可以从第一和第二微电子元件的导电层(610)延伸,并且组件的多个端子(616)可以与引线电连接。

    MICRO PIN GRID ARRAY WITH PIN MOTION ISOLATION
    3.
    发明申请
    MICRO PIN GRID ARRAY WITH PIN MOTION ISOLATION 审中-公开
    带PIN码隔离的微型鼠标阵列

    公开(公告)号:WO2005065238A3

    公开(公告)日:2009-03-26

    申请号:PCT/US2004043049

    申请日:2004-12-21

    Abstract: A microelectronic package (20) includes a microelectronic element (22) having faces and contacts (26), a flexible substrate (30) overlying and spaced from a first face (24) of the microelectronic element (22), and a plurality of conductive terminals (42) exposed at a surface of the flexible substrate. The conductive terminals (42) are electrically interconnected with the microelectronic element (22) and the flexible substrate (30) includes a gap (50) extending at least partially around at least one of the conductive terminals (42). In certain embodiments, the package includes a support layer, such as a compliant layer (48), disposed between the first face (24) of the microelectronic element (22) and the flexible substrate (30). In other embodiments, the support layer includes at least one opening that is at least partially aligned with one of the conductive terminals.

    Abstract translation: 微电子封装(20)包括具有面和触点(26)的微电子元件(22),覆盖并与微电子元件(22)的第一面(24)隔开的柔性衬底(30),以及多个导电 端子(42)暴露在柔性基板的表面。 导电端子(42)与微电子元件(22)电互连,并且柔性基板(30)包括至少部分地围绕至少一个导电端子(42)延伸的间隙(50)。 在某些实施例中,封装包括设置在微电子元件(22)的第一面(24)和柔性基板(30)之间的支撑层,例如顺应层(48)。 在其他实施例中,支撑层包括至少一个与导电端子之一至少部分对准的开口。

    STRUCTURE AND METHOD OF FORMING CAPPED CHIPS
    6.
    发明申请
    STRUCTURE AND METHOD OF FORMING CAPPED CHIPS 审中-公开
    结构及其形成方法

    公开(公告)号:WO2006020744A3

    公开(公告)日:2006-06-08

    申请号:PCT/US2005028492

    申请日:2005-08-11

    Abstract: As disclosed herein, structures and methods are provided for forming capped chips. As provided by the disclosed method, a metal base pattern (26) is formed on a chip (8) insulated from wiring (11) of the chip, and a cap (42) is formed including a metal. The cap (42) is joined to the metal base pattern (26) on the chip to form the capped chip (48). In one embodiment, a front surface (9) of the chip is exposed which extends from a contact (14) or (16) of the chip to an edge (13) of the chip (8). In another embodiment, a conductive connection is formed to the contact (14) or (16), the conductive connection extending from the contact to a terminal (46) at an exposed plane (49) above the front surface (9) of the chip (8).

    Abstract translation: 如本文所公开的,提供了用于形成加盖芯片的结构和方法。 如所公开的方法所示,在与芯片的布线(11)绝缘的芯片(8)上形成金属基底图案(26),并且形成包括金属的帽(42)。 帽(42)连接到芯片上的金属基底图案(26)以形成封盖芯片(48)。 在一个实施例中,芯片的前表面(9)暴露,其从芯片的接触件(14)或(16)延伸到芯片(8)的边缘(13)。 在另一个实施例中,导电连接形成于接触件(14)或(16),导电连接件在芯片的前表面(9)上方的暴露平面(49)处从接触件延伸到端子(46) (8)。

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