公开(公告)号：US20120153499A1

公开(公告)日：2012-06-21

申请号：US13244506

申请日：2011-09-25

申请人： Hak-Kyoon BYUN ,  Dae-Young CHOI ,  Mi-Yeon KIM

发明人： Hak-Kyoon BYUN ,  Dae-Young CHOI ,  Mi-Yeon KIM

IPC分类号： H01L23/48

CPC分类号： H01L23/49827 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17179 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.

摘要翻译： 提供半导体封装和封装封装。 半导体封装包括衬底; 安装在所述基板的表面上的半导体芯片; 设置在基板的表面上的连接导体; 形成在所述基板上并且设置有所述连接导体和所述半导体芯片的模具; 并且连接通过模具延伸的通孔并暴露连接导体。 对于连接通孔的第一连接通孔，由第一连接通孔露出的第一连接导体与第一连接通孔的入口之间的平面距离不均匀。

公开(公告)号：US20080160724A1

公开(公告)日：2008-07-03

申请号：US11945896

申请日：2007-11-27

申请人： Hyun-Jung SONG ,  Hak-Kyoon BYUN ,  Jong-Bo SHIM ,  Min-Ok NA

发明人： Hyun-Jung SONG ,  Hak-Kyoon BYUN ,  Jong-Bo SHIM ,  Min-Ok NA

IPC分类号： H01L21/304

CPC分类号： H01L21/6836 ,  B23K26/042 ,  B23K26/18 ,  B23K26/40 ,  B23K2103/50 ,  H01L21/02035 ,  H01L21/78 ,  H01L2221/68327

摘要： Provided is a method of dicing a wafer where a plurality of semiconductor device regions is formed on a front side of the wafer, the semiconductor device regions being separated by scribe lanes, the method comprising dicing the wafer by irradiating a laser beam on a backside of the wafer along the scribe lanes. A laser beam is irradiated from an opposite side of the semiconductor device regions of the wafer so that thermal influence on the semiconductor device regions is minimized to improve the strength of a semiconductor chip. Furthermore, a third tape is used to maintain an arrangement of the semiconductor chips so as to minimize adherence problems caused by the laser beam.

摘要翻译： 本发明提供一种切割晶片的方法，其中在晶片的正面形成有多个半导体器件区域，半导体器件区域被划线分隔开，该方法包括通过在背面侧照射激光束来对晶片进行切割 沿着划线的晶圆。 从晶片的半导体器件区域的相对侧照射激光束，使得对半导体器件区域的热影响最小化，以提高半导体芯片的强度。 此外，使用第三带来保持半导体芯片的布置，以便最小化由激光束引起的粘附问题。

公开(公告)号：US20070045828A1

公开(公告)日：2007-03-01

申请号：US11509641

申请日：2006-08-25

申请人： Heung-kyu Kwon ,  Se-nyun Kim ,  Tae-hun Kim ,  Jeong-o Ha ,  Hak-kyoon Byun ,  Sung-yong Park

发明人： Heung-kyu Kwon ,  Se-nyun Kim ,  Tae-hun Kim ,  Jeong-o Ha ,  Hak-kyoon Byun ,  Sung-yong Park

IPC分类号： H01L23/34

CPC分类号： H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Disclosed is a semiconductor device packaging technique that is capable of resolving a problem of instability of bonding wires when stacking a plurality of semiconductor chips. The technique is also capable of realizing a slim, light and small package. The semiconductor device package includes a substrate having a substrate pad on a surface thereof, one or more memory chips stacked on the substrate with each memory chip having a pad connected to a common pin receiving a common signal applied to all the memory chips, an interposer chip stacked on the substrate and having an interconnection wire connected to the memory chip pad, the common pin of each of the memory chips being electrically connected to the interconnection wire via the memory chip pad, and a logic chip stacked on the substrate and having a bypass circuit which electrically connects or disconnects the interconnection wire to or from the substrate pad.

摘要翻译： 公开了一种半导体器件封装技术，其能够在堆叠多个半导体芯片时解决接合线不稳定的问题。 该技术还能够实现纤细，轻巧和小包装。 半导体器件封装包括其表面上具有衬底焊盘的衬底，堆叠在衬底上的一个或多个存储器芯片，每个存储器芯片具有连接到接收施加到所有存储器芯片的公共信号的公共引脚的焊盘，插入器 芯片堆叠在基板上并具有连接到存储器芯片焊盘的互连线，每个存储器芯片的公共引脚经由存储器芯片焊盘电连接到互连线，以及堆叠在基板上的逻辑芯片， 旁路电路，其将互连线电连接到基板焊盘或从基板焊盘断开。

公开(公告)号：US08184449B2

公开(公告)日：2012-05-22

申请号：US12206355

申请日：2008-09-08

申请人： Jung-Do Lee ,  Hak-Kyoon Byun ,  Tae-Hun Kim ,  Sang-Uk Han ,  Seon-Hyang You

发明人： Jung-Do Lee ,  Hak-Kyoon Byun ,  Tae-Hun Kim ,  Sang-Uk Han ,  Seon-Hyang You

IPC分类号： H05K7/10 ,  H05K7/12

CPC分类号： H01L25/50 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/181 ,  Y10T29/49169 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An electronic device includes a lower electronic part including a lower substrate, a lower chip structure disposed on the lower substrate, and a lower molding layer covering the lower chip structure and having a recessed region in an upper surface of the lower molding layer, and an upper electronic part including an upper substrate disposed on the lower electronic part, and an upper chip structure projecting from the upper substrate, wherein the recessed region of the lower molding layer receives the upper chip structure.

摘要翻译： 电子设备包括下电子部件，其包括下基板，设置在下基板上的下芯片结构，以及覆盖下芯片结构的下成型层，并且在下成型层的上表面具有凹部， 上部电子部件，其包括设置在下部电子部件上的上部基板和从上部基板突出的上部芯片结构，其中下部成型层的凹部区域接收上部芯片结构。

公开(公告)号：US07795743B2

公开(公告)日：2010-09-14

申请号：US11539133

申请日：2006-10-05

申请人： Tae-Hun Kim ,  Hak-Kyoon Byun ,  Sung-Yong Park ,  Heung-Kyu Kwon

发明人： Tae-Hun Kim ,  Hak-Kyoon Byun ,  Sung-Yong Park ,  Heung-Kyu Kwon

IPC分类号： H01L23/48

CPC分类号： H05K3/3436 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K2201/09781 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/4554

摘要： A wiring substrate having variously sized ball pads, a semiconductor package including the wiring substrate, and a stack package using the semiconductor package, to improve board level reliability (BLR) of a semiconductor package or stack package mounted on a mother board are shown. Outer ball pads are formed to have relatively greater surface areas at the corners of the semiconductor package as compared to those at other areas and are formed to have the greatest surface area within a designable range. Additionally, occurrence of cracks may be inhibited at junctions of other solder balls by forming dummy solder pads at the outermost corners among the outer ball pads formed proximate to the corners of the wiring substrate. Stress arising during a board level reliability test is absorbed without product failure at junctions between the dummy solder pads and dummy solder balls.

摘要翻译： 示出了具有各种尺寸的球垫的布线基板，包括布线基板的半导体封装和使用半导体封装的堆叠封装，以提高安装在母板上的半导体封装或堆叠封装的电路板级可靠性（BLR）。 与其他区域相比，外球垫形成为在半导体封装的角部处具有相对较大的表面积，并且形成为具有可设计范围内的最大表面积。 此外，通过在靠近布线基板的角部形成的外球垫中的最外角处形成虚拟焊盘，可以抑制其它焊球的接合处的裂缝的发生。 在电路板级可靠性测试中产生的应力在虚拟焊盘和虚拟焊球之间的接合处被吸收而没有产品故障。

公开(公告)号：US07624498B2

公开(公告)日：2009-12-01

申请号：US11755170

申请日：2007-05-30

申请人： Youn-sung Ko ,  Hak-kyoon Byun ,  Jung-hwan Woo ,  Hyun-jung Song

发明人： Youn-sung Ko ,  Hak-kyoon Byun ,  Jung-hwan Woo ,  Hyun-jung Song

IPC分类号： B23P19/00 ,  H01L21/00

CPC分类号： H01L21/67132 ,  H01L21/67092 ,  Y10T29/41 ,  Y10T29/49815 ,  Y10T29/49819 ,  Y10T29/49824 ,  Y10T29/53091 ,  Y10T29/53187 ,  Y10T29/53274

摘要： An apparatus for and a method of detaching a semiconductor chip from a tape minimize the likelihood that the semiconductor chip will crack. The apparatus includes a holder, a first ejector having an upper end, and a second ejector whose upper end is disposed centrally of that of the first ejector. The holder has an upper portion and a through-hole extending through the upper portion. The ejectors have upper ends that are extendable and retractable out of and back into the holder via the through-hole in the upper portion of the holder. A tape to which at least one semiconductor chip is attached is set against the upper portion of the holder. The first ejector is extended a first distance from the holder to push the semiconductor chip upward. The second ejector is extended from the holder by a second distance larger than the first distance so as to push the semiconductor chip further upward. Thus, the tape is progressively detached from the semiconductor chip.

摘要翻译： 从半导体芯片上分离半导体芯片的方法和方法最小化了半导体芯片会破裂的可能性。 该装置包括保持器，具有上端的第一喷射器和其上端设置在第一喷射器的中心的第二喷射器。 保持器具有延伸穿过上部的上部和通孔。 喷射器具有可以通过保持器上部的通孔而延伸和缩回到保持器内的上端。 安装有至少一个半导体芯片的胶带抵靠着保持器的上部。 第一喷射器从保持器延伸第一距离以向上推半导体芯片。 第二喷射器从保持器延伸大于第一距离的第二距离，以将半导体芯片进一步向上推。 因此，磁带从半导体芯片逐渐分离。

公开(公告)号：US20140091463A1

公开(公告)日：2014-04-03

申请号：US13943037

申请日：2013-07-16

申请人： Hae-jung YU ,  Hak-kyoon BYUN ,  Kyung-tae NA ,  Seung-hun HAN ,  Tae-sung PARK ,  Choong-bin YIM

发明人： Hae-jung YU ,  Hak-kyoon BYUN ,  Kyung-tae NA ,  Seung-hun HAN ,  Tae-sung PARK ,  Choong-bin YIM

IPC分类号： H01L23/00

CPC分类号： H01L24/14 ,  H01L23/145 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

摘要： According to example embodiments of inventive concepts, a semiconductor package apparatus includes a first semiconductor package including a first substrate, a first solder resist layer on the first substrate, and a first sealing member that covers and protects the first solder resist layer, and a plurality of solder balls on the first substrate. The plurality of solder balls includes a first solder ball having a first height and a second solder ball having a second height that is different from the first height. The first sealing member includes holes that expose the solder balls.

摘要翻译： 根据发明构思的示例性实施例，半导体封装装置包括第一半导体封装，其包括第一衬底，第一衬底上的第一阻焊层和覆盖并保护第一阻焊层的第一密封构件，以及多个 的焊球在第一基板上。 多个焊球包括具有第一高度的第一焊球和具有与第一高度不同的第二高度的第二焊球。 第一密封构件包括露出焊球的孔。

公开(公告)号：US20120315726A1

公开(公告)日：2012-12-13

申请号：US13491055

申请日：2012-06-07

申请人： HAK-KYOON BYUN ,  Bu-Won Kim ,  Raehyung Do ,  JongBo Shim ,  Woodong Lee

发明人： HAK-KYOON BYUN ,  Bu-Won Kim ,  Raehyung Do ,  JongBo Shim ,  Woodong Lee

IPC分类号： H01L21/82

CPC分类号： H01L21/784 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/3178 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/80 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/03009 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/03903 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05558 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0566 ,  H01L2224/06135 ,  H01L2224/08145 ,  H01L2224/08148 ,  H01L2224/08155 ,  H01L2224/27009 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/80815 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/94 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2224/03 ,  H01L2924/01028 ,  H01L2224/27 ,  H01L2924/00 ,  H01L2224/05552

摘要： Provided are methods of manufacturing a semiconductor chip package. The method includes forming a plurality of semiconductor chips, each of which includes a semiconductor substrate having a front and back surfaces facing each other, a chip pad provided on the front surface of the semiconductor substrate, and an interconnection pattern extending from the chip pad along a sidewall of the semiconductor substrate, stacking the semiconductor chips such that the interconnection patterns of the semiconductor chips directly contact each other, and reflowing the interconnection patterns of the semiconductor chips to connect the stacked semiconductor chips with each other.

摘要翻译： 提供制造半导体芯片封装的方法。 该方法包括形成多个半导体芯片，每个半导体芯片包括具有彼此面对的正面和背面的半导体衬底，设置在半导体衬底的前表面上的芯片焊盘以及从芯片焊盘延伸的互连图案 半导体衬底的侧壁，堆叠半导体芯片，使得半导体芯片的互连图案直接相互接触，并且回流半导体芯片的互连图案以将堆叠的半导体芯片彼此连接。

公开(公告)号：US20100037445A1

公开(公告)日：2010-02-18

申请号：US12603913

申请日：2009-10-22

申请人： Youn-sung Ko ,  Hak-kyoon Byun ,  Jung-hwan Woo ,  Hyun-jung Song

发明人： Youn-sung Ko ,  Hak-kyoon Byun ,  Jung-hwan Woo ,  Hyun-jung Song

IPC分类号： B23P19/04

CPC分类号： H01L21/67132 ,  H01L21/67092 ,  Y10T29/49815 ,  Y10T29/49819 ,  Y10T29/49824 ,  Y10T29/53091 ,  Y10T29/53187 ,  Y10T29/53274

摘要： An apparatus for and a method of detaching a semiconductor chip from a tape minimize the likelihood that the semiconductor chip will crack. The apparatus includes a holder, a first ejector having an upper end, and a second ejector whose upper end is disposed centrally of that of the first ejector. The holder has an upper portion and a through-hole extending through the upper portion. The ejectors have upper ends that are extendable and retractable out of and back into the holder via the through-hole in the upper portion of the holder. A tape to which at least one semiconductor chip is attached is set against the upper portion of the holder. The first ejector is extended a first distance from the holder to push the semiconductor chip upward. The second ejector is extended from the holder by a second distance larger than the first distance so as to push the semiconductor chip further upward. Thus, the tape is progressively detached from the semiconductor chip.

摘要翻译： 从半导体芯片上分离半导体芯片的方法和方法最小化了半导体芯片会破裂的可能性。 该装置包括保持器，具有上端的第一喷射器和其上端设置在第一喷射器的中心的第二喷射器。 保持器具有延伸穿过上部的上部和通孔。 喷射器具有可以通过保持器上部的通孔而延伸和缩回到保持器内的上端。 安装有至少一个半导体芯片的胶带抵靠着保持器的上部。 第一喷射器从保持器延伸第一距离以向上推半导体芯片。 第二喷射器从保持器延伸大于第一距离的第二距离，以将半导体芯片进一步向上推。 因此，磁带从半导体芯片逐渐分离。

公开(公告)号：US20090085185A1

公开(公告)日：2009-04-02

申请号：US12238781

申请日：2008-09-26

申请人： Hak-Kyoon BYUN ,  Tae-Hun KIM ,  Sang-Uk HAN ,  Jung-Do LEE ,  Seon-Hyang YOU

发明人： Hak-Kyoon BYUN ,  Tae-Hun KIM ,  Sang-Uk HAN ,  Jung-Do LEE ,  Seon-Hyang YOU

IPC分类号： H01L23/538

CPC分类号： H01L25/105 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A stack-type semiconductor package, a method of forming the same, and an electronic system including the same are provided. The stack-type semiconductor package includes: a lower printed circuit board having a plurality of connection bumps disposed on an upper surface of the lower printed circuit board and a plurality of lower interconnections; at least one first lower chip sequentially stacked on the lower printed circuit board and electrically connected to the plurality of lower interconnections; a lower molding resin compound disposed on the lower printed circuit board and covering the first lower chips; a double-sided wiring board bonded to the lower molding resin compound and electrically connected to the connection bumps; and an upper chip package bonded to the double-sided wiring board and having upper bumps electrically connected to an interconnection pattern of the double-sided wiring board.

摘要翻译： 提供堆叠型半导体封装，其形成方法和包括该堆叠型半导体封装的电子系统。 堆叠型半导体封装包括：下印刷电路板，其具有设置在下印刷电路板的上表面上的多个连接凸块和多个下互连; 至少一个第一下部芯片，其顺序地堆叠在所述下部印刷电路板上并电连接到所述多个下部互连; 设置在下部印刷电路板上并覆盖第一下部芯片的下部成型树脂组合物; 与下模塑树脂复合物接合并与连接凸块电连接的双面布线板; 以及上芯片封装，其结合到所述双面布线板并且具有电连接到所述双面布线板的布线图案的上凸块。