公开(公告)号：US09859235B2

公开(公告)日：2018-01-02

申请号：US12619503

申请日：2009-11-16

申请人： Yu-Wen Liu ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Shin-Puu Jeng ,  Ying-Ju Chen ,  Shang-Yun Hou ,  Pei-Haw Tsao ,  Chen-Hua Yu

发明人： Yu-Wen Liu ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Shin-Puu Jeng ,  Ying-Ju Chen ,  Shang-Yun Hou ,  Pei-Haw Tsao ,  Chen-Hua Yu

IPC分类号： H01L23/488 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L24/05 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0215 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05566 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/00014 ,  H01L2924/2064 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599

摘要： A system and method for forming an underbump metallization (UBM) is presented. A preferred embodiment includes a raised UBM which extends through a passivation layer so as to make contact with a contact pad while retaining enough of the passivation layer between the contact pad and the UBM to adequately handle the peeling and shear stress that results from CTE mismatch and subsequent thermal processing. The UBM contact is preferably formed in either an octagonal ring shape or an array of contacts.

公开(公告)号：US09601443B2

公开(公告)日：2017-03-21

申请号：US11706940

申请日：2007-02-13

申请人： Hao-Yi Tsai ,  Shih-Hsun Hsu ,  Shih-Cheng Chang ,  Shang-Yun Hou ,  Hsien-Wei Chen ,  Chia-Lun Tsai ,  Benson Liu ,  Shin-Puu Jeng ,  Anbiarshy Wu

发明人： Hao-Yi Tsai ,  Shih-Hsun Hsu ,  Shih-Cheng Chang ,  Shang-Yun Hou ,  Hsien-Wei Chen ,  Chia-Lun Tsai ,  Benson Liu ,  Shin-Puu Jeng ,  Anbiarshy Wu

IPC分类号： H01L21/66 ,  H01L23/48 ,  H01L23/58 ,  H01L23/00

CPC分类号： H01L23/585 ,  H01L22/34 ,  H01L24/11 ,  H01L2224/0554 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor structure includes a daisy chain adjacent to an edge of a semiconductor chip. The daisy chain includes a plurality of horizontal metal lines distributed in a plurality of metallization layers, wherein the horizontal metal lines are serially connected; a plurality of connecting pads in a same layer and electrically connecting the horizontal metal lines, wherein the connecting pads are physically separated from each other; and a plurality of vertical metal lines, each connecting one of the connecting pads to one of the horizontal metal lines, wherein one of the plurality of connecting pads is connected to one of the plurality of horizontal metal lines by only one of the plurality of vertical metal lines; and a seal ring adjacent and electrically disconnected from the daisy chain.

公开(公告)号：US09093411B2

公开(公告)日：2015-07-28

申请号：US12984669

申请日：2011-01-05

申请人： Ying-Ju Chen ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii

发明人： Ying-Ju Chen ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii

IPC分类号： H01L21/66 ,  H01L23/00

CPC分类号： H01L22/34 ,  H01L22/32 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/5383 ,  H01L24/05 ,  H01L29/0649 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2924/00

摘要： A pad structure in a semiconductor wafer for wafer testing is described. The pad structure includes at least two metal pads connected there-between by a plurality of conductive visa in one or more insulation layers. A plurality of contact bars in contact with the bottom-most metal pad extends substantially vertically from the bottom-most metal pad into the substrate. An isolation structure substantially surrounds the plurality of contact bars to isolate the pad structure.

摘要翻译： 描述用于晶片测试的半导体晶片中的焊盘结构。 焊盘结构包括至少两个连接在其上的金属焊盘，其间通过一个或多个绝缘层中的多个导电签证。 与最底部的金属焊盘接触的多个接触棒从最底部的金属焊盘基本垂直地延伸到衬底中。 隔离结构基本上围绕多个接触杆以隔离垫结构。

公开(公告)号：US09000876B2

公开(公告)日：2015-04-07

申请号：US13419272

申请日：2012-03-13

申请人： Hao-Yi Tsai ,  Hsien-Wei Chen ,  Hung-Yi Kuo ,  Jie Chen ,  Ying-Ju Chen ,  Tsung-Yuan Yu

发明人： Hao-Yi Tsai ,  Hsien-Wei Chen ,  Hung-Yi Kuo ,  Jie Chen ,  Ying-Ju Chen ,  Tsung-Yuan Yu

IPC分类号： H01F5/00 ,  H01F27/28 ,  H01F27/36 ,  H01L31/107 ,  H01L23/522 ,  H01L23/552 ,  H01L23/00 ,  H01L49/02 ,  H01L23/58

CPC分类号： H01L23/5227 ,  H01L21/768 ,  H01L23/5225 ,  H01L23/552 ,  H01L23/585 ,  H01L24/03 ,  H01L24/11 ,  H01L28/10 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/06515 ,  Y10T29/4902

摘要： An inductor device and method of forming the inductor device are provided. In some embodiments the inductor device includes a post passivation interconnect (PPI) layer disposed and an under bump metallization (UBM) layer, each disposed over a substrate. The PPI layer forms a coil and dummy pads. The dummy pads are disposed around a substantial portion of the coil to shield the coil from electromagnetic interference. A first portion of the UBM layer is electrically coupled to the coil and configured to interface with an electrical coupling member.

摘要翻译： 提供一种形成电感器件的电感器件和方法。 在一些实施例中，电感器件包括设置在衬底上的后钝化互连（PPI）层和凸块下金属化（UBM）层。 PPI层形成线圈和虚拟垫。 虚拟焊盘围绕线圈的大部分设置，以屏蔽线圈免受电磁干扰。 UBM层的第一部分电耦合到线圈并且被配置为与电耦合构件相接合。

公开(公告)号：US08981580B2

公开(公告)日：2015-03-17

申请号：US13463433

申请日：2012-05-03

申请人： Shin-Puu Jeng ,  Yu-Wen Liu ,  Hao-Yi Tsai ,  Hsien-Wei Chen

发明人： Shin-Puu Jeng ,  Yu-Wen Liu ,  Hao-Yi Tsai ,  Hsien-Wei Chen

IPC分类号： H01L23/48 ,  H01L23/00

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/16 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2924/00

摘要： A bonding pad structure is provided that includes two conductive layers and a connective layer interposing the two conductive layers. The connective layer includes a contiguous, conductive structure. In an embodiment, the contiguous conductive structure is a solid layer of conductive material. In other embodiments, the contiguous conductive structure is a conductive network including, for example, a matrix configuration or a plurality of conductive stripes. At least one dielectric spacer may interpose the conductive network. Conductive plugs may interconnect a bond pad and one of the conductive layers.

摘要翻译： 提供了一种焊盘结构，其包括两个导电层和插入两个导电层的连接层。 连接层包括连续的导电结构。 在一个实施例中，邻接的导电结构是导电材料的固体层。 在其它实施例中，连续导电结构是包括例如矩阵配置或多个导电条纹的导电网络。 至少一个电介质间隔物可以插入导电网络。 导电插头可以将接合焊盘和导电层中的一个互连。

公开(公告)号：US08749043B2

公开(公告)日：2014-06-10

申请号：US13409756

申请日：2012-03-01

申请人： Chen-Hua Yu ,  Mirng-Ji Lii ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Kai-Chiang Wu

发明人： Chen-Hua Yu ,  Mirng-Ji Lii ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Kai-Chiang Wu

IPC分类号： H01L23/02 ,  H01L21/16

CPC分类号： H01L24/14 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/11011 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0206 ,  H05K1/0306 ,  H05K1/113 ,  H05K2201/068 ,  H01L2224/45099 ,  H01L2924/00012

摘要： A package on packaging structure comprising a first package and a second package provides for improved thermal conduction and mechanical strength by the introduction of a thermally conductive substrate attached to the second package. The first package has a first substrate and a first integrated circuit. The second package has a second substrate containing through vias that has a first coefficient of thermal expansion. The second package also has a second integrated circuit having a second coefficient of thermal expansion located on the second substrate. The second coefficient of thermal expansion deviates from the first coefficient of thermal expansion by less than about 10 or less than about 5 parts-per-million per degree Celsius. A first set of conductive elements couples the first substrate and the second substrate. A second set of conductive elements couples the second substrate and the second integrated circuit.

摘要翻译： 包装结构包括第一包装和第二包装通过引入连接到第二包装件上的导热基材提供改进的热传导和机械强度。 第一封装具有第一衬底和第一集成电路。 第二包装具有包含通孔的第二基板，其具有第一热膨胀系数。 第二封装还具有第二集成电路，其具有位于第二基板上的第二热膨胀系数。 第二热膨胀系数从第一热膨胀系数偏离每摄氏度小于约10或小于约5百万分之一。 第一组导电元件将第一基板和第二基板连接。 第二组导电元件将第二基板和第二集成电路耦合。

公开(公告)号：US20130277838A1

公开(公告)日：2013-10-24

申请号：US13452507

申请日：2012-04-20

申请人： Chen-Hua Yu ,  Hao-Yi Tsai ,  Chien-Hsiun Lee ,  Chung-Shi Liu ,  Hsien-Wei Chen

发明人： Chen-Hua Yu ,  Hao-Yi Tsai ,  Chien-Hsiun Lee ,  Chung-Shi Liu ,  Hsien-Wei Chen

IPC分类号： H01L21/60 ,  H01L23/498

CPC分类号： H01L24/11 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02125 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03464 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/06 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2224/05552 ,  H01L2924/00

摘要： Methods and apparatus for solder connections. An apparatus includes a substrate having a conductive terminal on a surface; a passivation layer overlying the surface of the substrate and the conductive terminal; an opening in the passivation layer exposing a portion of the conductive terminal; at least one stud bump bonded to the conductive terminal in the opening and extending in a direction normal to the surface of the substrate; and a solder connection formed on the conductive terminal in the opening and enclosing the at least one stud bump. Methods for forming the solder connections are disclosed.

摘要翻译： 焊接方法和装置。 一种装置包括：在表面上具有导电端子的基板; 覆盖在衬底表面上的钝化层和导电端子; 所述钝化层中的开口暴露所述导电端子的一部分; 至少一个凸起凸块，其结合到所述开口中的所述导电端子并且沿垂直于所述基板的表面的方向延伸; 以及形成在所述开口中的所述导电端子上并且包围所述至少一个螺柱凸块的焊接连接。 公开了形成焊料连接的方法。

公开(公告)号：US20130228932A1

公开(公告)日：2013-09-05

申请号：US13409756

申请日：2012-03-01

申请人： Chen-Hua Yu ,  Mirng-Ji Lii ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Kai-Chiang Wu

发明人： Chen-Hua Yu ,  Mirng-Ji Lii ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Kai-Chiang Wu

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L24/14 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/11011 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0206 ,  H05K1/0306 ,  H05K1/113 ,  H05K2201/068 ,  H01L2224/45099 ,  H01L2924/00012

摘要： A package on packaging structure comprising a first package and a second package provides for improved thermal conduction and mechanical strength by the introduction of a thermally conductive substrate attached to the second package. The first package has a first substrate and a first integrated circuit. The second package has a second substrate containing through vias that has a first coefficient of thermal expansion. The second package also has a second integrated circuit having a second coefficient of thermal expansion located on the second substrate. The second coefficient of thermal expansion deviates from the first coefficient of thermal expansion by less than about 10 or less than about 5 parts-per-million per degree Celsius. A first set of conductive elements couples the first substrate and the second substrate. A second set of conductive elements couples the second substrate and the second integrated circuit.

公开(公告)号：US08450126B2

公开(公告)日：2013-05-28

申请号：US13197003

申请日：2011-08-03

申请人： Hsien-Wei Chen ,  Ying-Ju Chen ,  Yu-Wen Liu ,  Hao-Yi Tsai ,  Shin-Puu Jeng

发明人： Hsien-Wei Chen ,  Ying-Ju Chen ,  Yu-Wen Liu ,  Hao-Yi Tsai ,  Shin-Puu Jeng

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： H01L22/34 ,  H01L24/05 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

摘要： A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer.

摘要翻译： 具有集成的模具隔离保护屏障的半导体测试焊盘互连结构。 互连结构包括多个堆叠的金属层，每个层具有通过介电材料层与其它测试焊盘分离的导电测试焊盘。 在一个实施例中，至少一个金属通孔条被嵌入到互连结构中，并将金属层中的每个测试焊盘电连接在一起。 在一些实施例中，通孔棒基本上沿着由每个测试垫限定的整个第一侧面延伸。 在其他实施例中，可以提供一对相对的通孔条，其布置在限定在半导体晶片上的划线带中的模切单切锯切线的相对侧上。

公开(公告)号：US08368180B2

公开(公告)日：2013-02-05

申请号：US12619464

申请日：2009-11-16

申请人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Hao-Yi Tsai ,  Shang-Yun Hou ,  Hsien-Wei Chen ,  Ming-Yen Chiu

发明人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Hao-Yi Tsai ,  Shang-Yun Hou ,  Hsien-Wei Chen ,  Ming-Yen Chiu

IPC分类号： H01L23/544

CPC分类号： H01L21/78

摘要： A system and method for preventing defaults during singulation is presented. An embodiment comprises a dummy metal structure located in the scribe region. The dummy metal structure comprises a series of alternating dummy lines that are connected through dummy vias. The dummy lines are offset from dummy lines in adjacent metal layers. Additionally, the dummy lines and dummy vias in the upper layers of the scribe line may be formed with larger dimensions than the dummy lines and dummy vias located in the lower layers.

摘要翻译： 提出了一种在分割过程中防止违约的系统和方法。 一个实施例包括位于划线区域中的虚拟金属结构。 虚拟金属结构包括通过虚拟通孔连接的一系列交替虚拟线。 伪线与相邻金属层中的虚拟线偏移。 此外，划线的上层中的虚拟线和虚拟通路可以形成为具有比位于下层中的虚拟线和虚拟通孔更大的尺寸。