公开(公告)号：US11683887B2

公开(公告)日：2023-06-20

申请号：US17506045

申请日：2021-10-20

Applicant: Dell Products L.P.

Inventor： Malikarjun Vasa ,  Sanjay Kumar ,  Bhyrav Mutnury

IPC: H05K1/18 ,  H05K1/02

CPC classification number: H05K1/182 ,  H05K1/0218 ,  H05K1/0237 ,  H05K2201/0183 ,  H05K2201/10621

Abstract: An add-in card printed circuit board (PCB) includes a body portion and a card edge portion. The body portion includes a circuit trace associated with a high-speed data communication interface. The card edge portion includes contact fingers, and is configured to be inserted into a card edge connector of an information handling system. The contact fingers include a signal contact finger coupled to the circuit trace, and a ground contact finger that is located adjacent to the signal contact finger. The ground contact finger includes a ground via that couples the ground contact finger to a ground plane layer of the add-in card PCB. The ground via is located half way within the body portion and half way within the card edge portion.

公开(公告)号：US20230354525A1

公开(公告)日：2023-11-02

申请号：US17624355

申请日：2021-05-06

Applicant: INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.

Inventor： Weigang YAO ,  Chunhua ZHOU

IPC: H05K1/18 ,  H01L23/498 ,  H01L23/31 ,  H01L23/367 ,  H05K1/02 ,  H05K1/11 ,  H05K3/32 ,  H01L21/48

CPC classification number: H05K1/183 ,  H01L21/4853 ,  H01L23/3107 ,  H01L23/3672 ,  H01L23/49811 ,  H01L23/49844 ,  H05K1/021 ,  H05K1/111 ,  H05K1/184 ,  H05K3/325 ,  H05K2201/1059 ,  H05K2201/10621

Abstract: The present disclosure provides a semiconductor module comprising a semiconductor device removably pressed-fit in a cavity formed in a printed circuit board and methods for manufacturing the same. The semiconductor device and the cavity of the printed circuit board can cooperate with each other and act as an electrical plug and an electrical socket respectively. Soldering the semiconductor device on the printed circuit board can be avoided. Therefore, the packaging process can be more flexible and reliability issues with solder joints can be eliminated. Moreover, heatsink can be mounted on top and/or bottom of the semiconductor device after being received in the cavity of the printed circuit board. Thermal dissipation efficiency can be greatly enhanced.

公开(公告)号：US20180138611A1

公开(公告)日：2018-05-17

申请号：US15619605

申请日：2017-06-12

Applicant: LEAR CORPORATION

Inventor： Montserrat Piñol Pedret ,  Ferran Juanes Ribas ,  Primitivo Aznar ,  Enric Aparicio Rollan

IPC: H01R12/70 ,  H05K3/34 ,  H01R12/71 ,  H01R43/02 ,  H01R24/66 ,  H05K1/11 ,  H05K1/02

CPC classification number: H01R12/7052 ,  H01R12/51 ,  H01R12/7064 ,  H01R12/707 ,  H01R12/7082 ,  H01R12/716 ,  H01R12/718 ,  H01R24/66 ,  H01R43/0256 ,  H01R43/0263 ,  H05K1/0289 ,  H05K1/111 ,  H05K3/341 ,  H05K2201/10621

Abstract: The present disclosure includes an adjustable circuit board assembly including a circuit board, a header connected to the circuit board, and a matrix connector. The header may be configured for connection with the circuit board via a connection matrix and the matrix connector. A method of manufacturing a circuit board assembly may include providing a circuit board, providing a terminal header having a plurality of terminals, providing a connection matrix to at least one of the circuit board and the terminal header, providing a matrix connector, connecting the terminal header with the circuit board via the matrix connector and the connection matrix, and connecting the plurality of terminals to the circuit board.

公开(公告)号：US20160073504A1

公开(公告)日：2016-03-10

申请号：US14784124

申请日：2014-04-23

Applicant: HITACHI AUTOMOTIVE SYSTEMS, LTD.

Inventor： Miki HIRAOKA ,  Shiro YAMASHITA ,  Tomishige YATSUGI

IPC: H05K1/18 ,  H05K1/11

CPC classification number: H05K1/181 ,  H05K1/111 ,  H05K3/3442 ,  H05K2201/09381 ,  H05K2201/09427 ,  H05K2201/09663 ,  H05K2201/10621 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

Abstract: The objective of the present invention is to improve reliability in a solder connection portion between an electronic component and a wiring pattern. A pair of wiring patterns (31A and 31B) are formed on a circuit wiring board (30) with an insulation layer (37) therebetween. Each wiring pattern (31A and 31B) has a land (33a or 33b) and a wiring portion (34a or 34b) that is narrower than the land. By way of solder (42), a chip component (41) is soldered to the lands (33a and 33b). The x (width) direction center (Xa) of each connection portion (53) where a respective wiring portion (34a or 34b) is connected to a respective land (33a or 33b) is disposed at a position that is outside of both the region in which a region of predetermined width (Wc) of the chip component (41) extends in the x (longitudinal) direction, and the region in which a region of predetermined length (Lc) of the chip component (41) extends in a y (transverse) direction.

Abstract translation: 本发明的目的是提高电子部件与布线图形之间的焊接连接部的可靠性。 一对布线图案（31A和31B）形成在其间具有绝缘层（37）的电路布线板（30）上。 每个布线图案（31A和31B）具有比平台窄的区域（33a或33b）和布线部分（34a或34b）。 通过焊料（42），将芯片部件（41）焊接到焊盘（33a和33b）上。 其中各个配线部分（34a或34b）连接到相应的焊盘（33a或33b）的每个连接部分（53）的x（宽度）方向中心（Xa）被布置在两个区域 其中芯片部件（41）的预定宽度（Wc）的区域在x（纵向）方向上延伸，并且芯片部件（41）的预定长度（Lc）的区域在a 横向）方向。

公开(公告)号：US20150366052A1

公开(公告)日：2015-12-17

申请号：US14303396

申请日：2014-06-12

Applicant: Shaowu HUANG ,  John J. ABBOTT

Inventor： Shaowu HUANG ,  John J. ABBOTT

IPC: H05K1/02 ,  H05K3/40 ,  H05K1/11

CPC classification number: H05K1/024 ,  H01R12/71 ,  H01R13/6598 ,  H05K1/0234 ,  H05K1/115 ,  H05K1/116 ,  H05K3/4038 ,  H05K3/4647 ,  H05K2201/10621 ,  Y10T29/49156 ,  Y10T29/49167

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect stub. In one instance, a printed circuit board (PCB) assembly may comprise a substrate and an interconnect (such as a via) formed in the substrate to route an electrical signal within the PCB. The interconnect may include a stub formed on the interconnect. At least a portion of the stub may be covered with an absorbing material to at least partially absorb a portion of the electric signal that is reflected by the stub. The absorbing material may be selected such that its dielectric loss tangent is greater than one, for a frequency range of a frequency of the reflected portion of the electric signal. A dielectric constant of the absorbing material may be inversely proportionate to the frequency of the reflected electric signal. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于互连短截线中的电信号吸收的技术和配置。 在一种情况下，印刷电路板（PCB）组件可以包括衬底和形成在衬底中以在PCB内布置电信号的互连（例如通孔）。 互连可以包括形成在互连上的短截线。 短截线的至少一部分可以用吸收材料覆盖以至少部分地吸收被短截线反射的电信号的一部分。 对于电信号的反射部分的频率的频率范围，可以选择吸收材料使得其介电损耗角正切大于1。 吸收材料的介电常数可以与反射电信号的频率成反比。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20140159990A1

公开(公告)日：2014-06-12

申请号：US13711190

申请日：2012-12-11

Applicant: OPTICON SENSORS EUROPE B.V.

Inventor： Alexander Azhari

IPC: H01Q1/22 ,  H01P11/00

CPC classification number: H01Q1/088 ,  H01Q1/38 ,  H01Q9/0421 ,  H05K3/303 ,  H05K3/3415 ,  H05K2201/0311 ,  H05K2201/10098 ,  H05K2201/10265 ,  H05K2201/10568 ,  H05K2201/10621 ,  Y02P70/613 ,  Y10T29/49016 ,  Y10T29/49018

Abstract: An electronic circuit that needs to transmit or receive radio waves achieves that goal by using an antenna. This disclosure teaches an antenna that can be mounted on an edge of a circuit board. This disclosure teaches antenna shapes that, when mounted on an edge of a circuit board, can advantageously make contact with circuits on both sides of the board. Some antenna shapes have protruding portions with springiness that facilitates affixing the antenna to the board and facilitates reliable electrical contacts with the circuits. The disclosure also teaches methods for mounting an antenna on an edge of a circuit board.

Abstract translation: 需要发送或接收无线电波的电子电路通过使用天线来实现该目的。 本公开教导了可以安装在电路板的边缘上的天线。 本公开教导了当安装在电路板的边缘上时可以有利地与电路两侧的电路接触的天线形状。 一些天线形状具有弹性的突出部分，其有利于将天线固定到板上并且促进与电路的可靠的电接触。 本公开还教导了将天线安装在电路板的边缘上的方法。

公开(公告)号：US12058805B2

公开(公告)日：2024-08-06

申请号：US17447750

申请日：2021-09-15

Applicant: Hella GmbH & Co. KGaA

Inventor： Joël Afanou ,  Olivier Vilain

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/021 ,  H05K1/182 ,  H05K2201/10015 ,  H05K2201/10621

Abstract: An electrical apparatus is provided with a power semiconductor module, at least one capacitor, a circuit carrier, and a first heat sink. The power semiconductor module and the circuit carrier are arranged on the first heat sink. The electrical apparatus comprises a second heat sink arranged on the power semiconductor module and connected to the first heat sink.

公开(公告)号：US20190067180A1

公开(公告)日：2019-02-28

申请号：US16110121

申请日：2018-08-23

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： David AUCHERE ,  Laurent SCHWARZ ,  Deborah COGONI ,  Eric SAUGIER

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/13 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/561 ,  H01L21/78 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/00 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/16235 ,  H05K1/185 ,  H05K2201/10621 ,  H05K2201/10636

Abstract: An electronic device includes a support wafer, an electronic chip and an encapsulating block for the electronic chip above the support wafer. The support wafer is provided with a first network of electrical connections and a second network of electrical connections formed solely by tracks. First electrical connection elements are interposed between first front electrical contacts of the electronic chip and rear electrical contacts of the first network. Second electrical connection elements are interposed between second front electrical contacts of the electronic chip and internal electrical contact zones of the tracks of the second network. The first network includes front external electrical contacts and the tracks exhibiting external electrical contact zones.

公开(公告)号：US09814130B2

公开(公告)日：2017-11-07

申请号：US15138880

申请日：2016-04-26

Applicant: Intel Corporation

Inventor： Shaowu Huang ,  John J. Abbott

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/40 ,  H05K3/46 ,  H01R12/71 ,  H01R13/6598

CPC classification number: H05K1/024 ,  H01R12/71 ,  H01R13/6598 ,  H05K1/0234 ,  H05K1/115 ,  H05K1/116 ,  H05K3/4038 ,  H05K3/4647 ,  H05K2201/10621 ,  Y10T29/49156 ,  Y10T29/49167

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect stub. In one instance, a printed circuit board (PCB) assembly may comprise a substrate and an interconnect (such as a via) formed in the substrate to route an electrical signal within the PCB. The interconnect may include a stub formed on the interconnect. At least a portion of the stub may be covered with an absorbing material to at least partially absorb a portion of the electric signal that is reflected by the stub. The absorbing material may be selected such that its dielectric loss tangent is greater than one, for a frequency range of a frequency of the reflected portion of the electric signal. A dielectric constant of the absorbing material may be inversely proportionate to the frequency of the reflected electric signal. Other embodiments may be described and/or claimed.

公开(公告)号：US20150061129A1

公开(公告)日：2015-03-05

申请号：US14475249

申请日：2014-09-02

Applicant: Senju Metal Industry Co., Ltd.

Inventor： Takahiro Hattori ,  Daisuke Soma ,  lsamu Sato

IPC: H01L23/00 ,  B23K1/20

CPC classification number: B23K1/203 ,  B23K1/0016 ,  B23K1/20 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03828 ,  H01L2224/1112 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13117 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13123 ,  H01L2224/13124 ,  H01L2224/13138 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13149 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/1316 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/1317 ,  H01L2224/13171 ,  H01L2224/13179 ,  H01L2224/1318 ,  H01L2224/1319 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13605 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13616 ,  H01L2224/13617 ,  H01L2224/13618 ,  H01L2224/1362 ,  H01L2224/13624 ,  H01L2224/13638 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1366 ,  H01L2224/13671 ,  H01L2924/3651 ,  H01L2924/384 ,  H05K3/3436 ,  H05K2201/10234 ,  H05K2201/10621 ,  H05K2201/10734 ,  H05K2203/041 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01032 ,  H01L2924/01014 ,  H01L2924/01057 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01015

Abstract: A bump electrode is formed on an electrode pad using a Cu core ball in which a core material is covered with solder plating, and a board which has bump electrodes such as semiconductor chip or printed circuit board mounts such a bump electrode. Flux is coated on a substrate and the bump electrodes are then mounted on the electrode pad. In a step of heating the electrode pad and the Cu core ball to melt the solder plating, a heating rate of the substrate is set to have not less than 0.01° C./sec and less than 0.3.

Abstract translation: 在电极焊盘上使用Cu芯球形成突起电极，其中芯材被焊料覆盖，并且具有诸如半导体芯片或印刷电路板的凸起电极的板安装这样的凸块电极。 将焊剂涂覆在衬底上，然后将凸块电极安装在电极焊盘上。 在加热电极焊盘和Cu芯球以熔化焊料镀层的步骤中，将衬底的加热速率设定为不低于0.01℃/秒且小于0.3。