公开(公告)号：US09799778B2

公开(公告)日：2017-10-24

申请号：US15157776

申请日：2016-05-18

Applicant: XINTEC INC.

Inventor： Yi-Ying Kuo ,  Ming-Chieh Huang ,  Hsi-Chien Lin

IPC: H01L31/02 ,  H01L31/18 ,  H01L31/0216

CPC classification number: H01L31/02002 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/562 ,  H01L31/0216 ,  H01L31/186 ,  H01L2224/11

Abstract: A chip package includes a chip, an insulating layer, a flowing insulating material layer and conductive layer. The chip has a conductive pad, a side surface, a first surface and a second surface opposite to the first surface, which the side surface is between the first surface and the second surface, and the conductive is below the first surface and protruded from the side surface. The insulating layer covers the second surface and the side surface, and the flowing insulating material layer is disposed below the insulating layer, and the flowing insulating material layer has a trench exposing the conductive pad protruded form the side surface. The conductive layer is disposed below the flowing insulating material layer and extended into the trench to contact the conductive pad.

公开(公告)号：US09780251B2

公开(公告)日：2017-10-03

申请号：US15451202

申请日：2017-03-06

Applicant: XINTEC INC.

Inventor： Wei-Luen Suen ,  Wei-Ming Chien ,  Po-Han Lee ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L31/18 ,  H01L31/02 ,  H01L31/0203 ,  H01L31/0236

CPC classification number: H01L31/02327 ,  H01L21/561 ,  H01L23/3114 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/02363 ,  H01L31/1804 ,  H01L2224/11

Abstract: A semiconductor structure includes a silicon substrate, a protection layer, an electrical pad, an isolation layer, a redistribution layer, a conductive layer, a passivation layer, and a conductive structure. The silicon substrate has a concave region, a step structure, a tooth structure, a first surface, and a second surface opposite to the first surface. The step structure and the tooth structure surround the concave region. The step structure has a first oblique surface, a third surface, and a second oblique surface facing the concave region and connected in sequence. The protection layer is located on the first surface of the silicon substrate. The electrical pad is located in the protection layer and exposed through the concave region. The isolation layer is located on the first and second oblique surfaces, the second and third surfaces of the step structure, and the tooth structure.

公开(公告)号：US09711469B2

公开(公告)日：2017-07-18

申请号：US14715445

申请日：2015-05-18

Applicant: XINTEC INC.

Inventor： Geng-Peng Pan ,  Yi-Ming Chang ,  Chia-Sheng Lin

IPC: H01L23/00 ,  H01L21/033 ,  H01L21/302 ,  H01L23/48 ,  H01L21/268 ,  H01L21/48 ,  H01L21/768

CPC classification number: H01L24/03 ,  H01L21/0273 ,  H01L21/0334 ,  H01L21/268 ,  H01L21/302 ,  H01L21/48 ,  H01L21/481 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L2224/0231 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/03831 ,  H01L2224/05017 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2924/00014

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first isolation layer is formed on a first surface of a wafer substrate. A conductive pad is formed on the first isolation layer. A hollow region through the first surface and a second surface of the wafer substrate is formed, such that the first isolation layer is exposed through the hollow region. A laser etching treatment is performed on the first isolation layer that is exposed through the hollow region, such that a first opening is formed in the first isolation layer, and a concave portion exposed through the first opening is formed in the conductive pad.

公开(公告)号：US09704772B2

公开(公告)日：2017-07-11

申请号：US15008241

申请日：2016-01-27

Applicant: XINTEC INC.

Inventor： Chien-Hung Liu

IPC: H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H05K1/18 ,  H05K1/02 ,  H05K1/11 ,  H05K3/32 ,  G06K9/00 ,  G01L19/14 ,  G06F21/32 ,  H01L21/02 ,  G01L19/00 ,  G01L19/06 ,  H01L23/525 ,  H01L21/60

CPC classification number: H01L23/3192 ,  G01L19/0061 ,  G01L19/06 ,  G01L19/14 ,  G06F21/32 ,  G06K9/00 ,  G06K9/00006 ,  H01L21/0212 ,  H01L21/02263 ,  H01L21/56 ,  H01L23/291 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/525 ,  H01L2021/60022 ,  H01L2224/11 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/181 ,  H05K3/32

Abstract: A chip package includes a chip, a dam layer, a permanent adhesive layer, a support, a buffer layer, a redistribution layer, a passivation layer, and a conducting structure. A conducting pad and a sensing device of the chip are located on a first surface of a substrate of the chip, and the conducting pad protrudes from the side surface of the substrate. The dam layer surrounds the sensing device. The permanent adhesive layer is between the support and the substrate. The support and the permanent adhesive layer have a trench to expose the conducting pad. The buffer layer is located on the support. The redistribution layer is located on the buffer layer and on the support, the permanent adhesive layer, and the conducting pad facing the trench. The passivation layer covers the redistribution layer, the buffer layer, and the conducting pad.

公开(公告)号：US20170179330A1

公开(公告)日：2017-06-22

申请号：US15451202

申请日：2017-03-06

Applicant: XINTEC INC.

Inventor： Wei-Luen SUEN ,  Wei-Ming CHIEN ,  Po-Han LEE ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L31/18 ,  H01L31/0203 ,  H01L31/0236 ,  H01L31/02

CPC classification number: H01L31/02327 ,  H01L21/561 ,  H01L23/3114 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/02363 ,  H01L31/1804 ,  H01L2224/11

Abstract: A semiconductor structure includes a silicon substrate, a protection layer, an electrical pad, an isolation layer, a redistribution layer, a conductive layer, a passivation layer, and a conductive structure. The silicon substrate has a concave region, a step structure, a tooth structure, a first surface, and a second surface opposite to the first surface. The step structure and the tooth structure surround the concave region. The step structure has a first oblique surface, a third surface, and a second oblique surface facing the concave region and connected in sequence. The protection layer is located on the first surface of the silicon substrate. The electrical pad is located in the protection layer and exposed through the concave region. The isolation layer is located on the first and second oblique surfaces, the second and third surfaces of the step structure, and the tooth structure.

公开(公告)号：US20170148752A1

公开(公告)日：2017-05-25

申请号：US15351309

申请日：2016-11-14

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Chia-Sheng LIN ,  Po-Han LEE ,  Wei-Luen SUEN

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/02 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/0214 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/0231 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05016 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2924/01013 ,  H01L2924/06 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A chip package includes a substrate, an isolation layer, a redistribution layer, a passivation layer, a first conductive layer, a second conductive layer, and a conductive structure. The isolation layer is located on the substrate. The redistribution layer is located on the isolation layer. The passivation layer is located on the isolation layer and the redistribution layer. The passivation layer has an opening, a wall surface that surrounds the opening, and a surface that faces away from the isolation layer. A portion of the redistribution layer is exposed through the opening. The first conductive layer is located on the redistribution layer that is in the opening, and extends to the wall surface and the surface of the passivation layer. The second conductive layer covers the first conductive layer. The conductive structure is located on the second conductive layer and protrudes from the passivation layer.

公开(公告)号：US09640405B2

公开(公告)日：2017-05-02

申请号：US14983401

申请日：2015-12-29

Applicant: XINTEC INC.

Inventor： Ying-Nan Wen ,  Chien-Hung Liu ,  Shih-Yi Lee ,  Ho-Yin Yiu

IPC: H01L23/00 ,  H01L21/304 ,  H01L21/76 ,  H01L21/78 ,  H01L21/683 ,  H01L21/268 ,  H01L21/768 ,  H01L23/498 ,  H01L23/48

CPC classification number: H01L24/02 ,  H01L21/268 ,  H01L21/304 ,  H01L21/31127 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76 ,  H01L21/76802 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L27/14678 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/03002 ,  H01L2224/0311 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014

Abstract: A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.

公开(公告)号：US20170117242A1

公开(公告)日：2017-04-27

申请号：US15297490

申请日：2016-10-19

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Po-Han LEE ,  Chi-Chang LIAO

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/06181 ,  H01L2224/08265 ,  H01L2224/1403 ,  H01L2224/14155 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/171 ,  H01L2224/29011 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/146

Abstract: A chip package is provided. The chip package includes a substrate. The substrate includes a sensing region or device region. The chip package also includes a first conducting structure disposed on the substrate. The first conducting structure is electrically connected to the sensing region or device region. The chip package further includes a passive element vertically stacked on the substrate. The passive element and the first conducting structure are positioned side by side.

公开(公告)号：US20170116458A1

公开(公告)日：2017-04-27

申请号：US15297546

申请日：2016-10-19

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Ying-Nan WEN ,  Chi-Chang LIAO ,  Yu-Lung HUANG

IPC: G06K9/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/08 ,  H01L21/78 ,  H01L23/31 ,  H01L23/04 ,  H01L21/683 ,  H01L21/56

CPC classification number: G06K9/00013 ,  G06K19/0716 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76895 ,  H01L21/78 ,  H01L23/04 ,  H01L23/08 ,  H01L23/15 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3135 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/0579 ,  H01L2224/058 ,  H01L2224/11002 ,  H01L2224/1132 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2924/351 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: A method for forming a sensing device includes providing a first substrate. The first substrate has a first surface and a second surface opposite thereto. A sensing region is adjacent to the first surface. A temporary cover plate is provided on the second surface to cover the sensing region. The method also includes forming a redistribution layer on the second surface and electrically connected to the sensing region. The method further includes removing the temporary cover plate after the formation of the redistribution layer. The first substrate is bonded to a second substrate and a cover plate after the removal of the temporary cover plate so that the first substrate is positioned between the second substrate and the cover plate. In addition, the method includes filling an encapsulating layer between the second substrate and the cover plate to surround the first substrate.

公开(公告)号：US20170110495A1

公开(公告)日：2017-04-20

申请号：US15277184

申请日：2016-09-27

Applicant: XINTEC INC.

Inventor： Jyun-Liang WU ,  Chia-Sheng LIN ,  Po-Han LEE ,  Yen-Shih HO

IPC: H01L27/146 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L27/14618 ,  H01L21/563 ,  H01L24/03 ,  H01L24/08 ,  H01L2224/0231 ,  H01L2224/0237

Abstract: A chip package includes a chip, a dam element, and a height-increasing element. The chip has an image sensing area, a first surface, and a second surface opposite to the first surface. The image sensing area is located on the first surface of the chip. The dam element is located on the first surface of the chip and surrounds the image sensing area. The height-increasing element is located on the dam element, such that the dam element is between the height-increasing element and the chip.