公开(公告)号：US20130119533A1

公开(公告)日：2013-05-16

申请号：US13297992

申请日：2011-11-16

Applicant: Chih-Hao Chen ,  Long Hua Lee ,  Chun-Hsing Su ,  Yi-Lin Tsai ,  Kung-Chen Yeh ,  Chung Yu Wang ,  Jui-Pin Hung ,  Jing-Cheng Lin

Inventor： Chih-Hao Chen ,  Long Hua Lee ,  Chun-Hsing Su ,  Yi-Lin Tsai ,  Kung-Chen Yeh ,  Chung Yu Wang ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC: H01L23/48 ,  H01L21/78

CPC classification number: H01L21/563 ,  H01L21/561 ,  H01L21/78 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/26145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/0665

Abstract: A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.

Abstract translation: 晶片级封装包括结合在支撑晶片上的半导体管芯。 半导体管芯在其衬底上至少有一个台阶凹槽。 在半导体管芯和支撑晶片之间形成底部填充层。 此外，底部填充层的高度受到台阶凹槽的限制。 在晶片级封装的制造过程中，台阶凹槽有助于减小晶片级封装上的应力。

公开(公告)号：US20130087920A1

公开(公告)日：2013-04-11

申请号：US13270776

申请日：2011-10-11

Applicant: Shin-Puu Jeng ,  Chen-Hua Yu ,  Jing-Cheng Lin

Inventor： Shin-Puu Jeng ,  Chen-Hua Yu ,  Jing-Cheng Lin

IPC: H01L23/488 ,  H01L21/50

CPC classification number: H01L24/16 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13025 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/16258 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/05552

Abstract: An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface. The first die is attached to the first surface of the substrate by first electrical connectors. The second die is attached to the first surface of the substrate by second electrical connectors. A size of one of the second electrical connectors is smaller than a size of one of the first electrical connectors.

Abstract translation: 实施例是包括基板，第一模具和第二模具的结构。 衬底具有第一表面。 第一模具通过第一电连接器附接到基板的第一表面。 第二模具通过第二电连接器附接到基板的第一表面。 第二电连接器之一的尺寸小于第一电连接器之一的尺寸。

公开(公告)号：US08395215B2

公开(公告)日：2013-03-12

申请号：US13351824

申请日：2012-01-17

Applicant: Jing-Cheng Lin

Inventor： Jing-Cheng Lin

IPC: H01L29/78

CPC classification number: H01L29/7833 ,  H01L21/02175 ,  H01L21/28255 ,  H01L29/16 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659

Abstract: Germanium field effect transistors and methods of fabricating them are described. In one embodiment, the method includes forming a germanium oxide layer over a substrate and forming a metal oxide layer over the germanium oxide layer. The germanium oxide layer and the metal oxide layer are converted into a first dielectric layer. A first electrode layer is deposited over the first dielectric layer.

Abstract translation: 描述锗场效应晶体管及其制造方法。 在一个实施例中，该方法包括在衬底上形成氧化锗层并在氧化锗层上形成金属氧化物层。 氧化锗层和金属氧化物层被转换为第一电介质层。 第一电极层沉积在第一介电层上。

公开(公告)号：US08338884B2

公开(公告)日：2012-12-25

申请号：US12708711

申请日：2010-02-19

Applicant: Jing-Cheng Lin ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L21/00

CPC classification number: H01L21/02494 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02587 ,  H01L21/02639 ,  H01L21/76224 ,  H01L29/165 ,  H01L29/267

Abstract: A semiconductor device includes a substrate formed of a first semiconductor material; two insulators on the substrate; and a semiconductor region having a portion between the two insulators and over the substrate. The semiconductor region has a bottom surface contacting the substrate and having sloped sidewalls. The semiconductor region is formed of a second semiconductor material different from the first semiconductor material.

Abstract translation: 半导体器件包括由第一半导体材料形成的衬底; 基板上有两个绝缘子; 以及半导体区域，其具有在所述两个绝缘体之间并且在所述衬底上的部分。 半导体区域具有与衬底接触并具有倾斜侧壁的底表面。 半导体区域由与第一半导体材料不同的第二半导体材料形成。

公开(公告)号：US20120238057A1

公开(公告)日：2012-09-20

申请号：US13488188

申请日：2012-06-04

Applicant: Hsien-Pin Hu ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

Inventor： Hsien-Pin Hu ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

IPC: H01L21/60

CPC classification number: H01L21/561 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.

公开(公告)号：US08124513B2

公开(公告)日：2012-02-28

申请号：US12630652

申请日：2009-12-03

Applicant: Jing-Cheng Lin

Inventor： Jing-Cheng Lin

IPC: H01L29/78

CPC classification number: H01L29/7833 ,  H01L21/02175 ,  H01L21/28255 ,  H01L29/16 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659

Abstract: Germanium field effect transistors and methods of fabricating them are described. In one embodiment, the method includes forming a germanium oxide layer over a substrate and forming a metal oxide layer over the germanium oxide layer. The germanium oxide layer and the metal oxide layer are converted into a first dielectric layer. A first electrode layer is deposited over the first dielectric layer.

Abstract translation: 描述锗场效应晶体管及其制造方法。 在一个实施例中，该方法包括在衬底上形成氧化锗层并在氧化锗层上形成金属氧化物层。 氧化锗层和金属氧化物层被转换为第一电介质层。 第一电极层沉积在第一介电层上。

公开(公告)号：US20120028411A1

公开(公告)日：2012-02-02

申请号：US12880736

申请日：2010-09-13

Applicant: Chen-Hua Yu ,  Jing-Cheng Lin

Inventor： Chen-Hua Yu ,  Jing-Cheng Lin

IPC: H01L21/50

CPC classification number: H01L24/81 ,  H01L21/561 ,  H01L21/568 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0655 ,  H01L2221/68327 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/13 ,  H01L2224/19 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method includes providing a carrier with an adhesive layer disposed thereon; and providing a die including a first surface, a second surface opposite the first surface. The die further includes a plurality of bond pads adjacent the second surface; and a dielectric layer over the plurality of bond pads. The method further includes placing the die on the adhesive layer with the first surface facing toward the adhesive layer and dielectric layer facing away from the adhesive layer; forming a molding compound to cover the die, wherein the molding compound surrounds the die; removing a portion of the molding compound directly over the die to expose the dielectric layer; and forming a redistribution line above the molding compound and electrically coupled to one of the plurality of bond pads through the dielectric layer.

Abstract translation: 一种方法包括提供载体上设置有粘合层; 以及提供包括第一表面，与第一表面相对的第二表面的模具。 模具还包括与第二表面相邻的多个接合焊盘; 以及多个接合焊盘上的介电层。 该方法还包括将模具放置在粘合剂层上，其中第一表面面向粘合剂层，电介质层背向粘合剂层; 形成模塑料以覆盖模具，其中模塑料围绕模具; 将模塑料的一部分直接在模具上去除以暴露介电层; 以及在所述模制化合物上形成再分配线，并通过所述介电层电耦合到所述多个键合焊盘之一。

公开(公告)号：US20110316147A1

公开(公告)日：2011-12-29

申请号：US12823851

申请日：2010-06-25

Applicant: Ying-Ching Shih ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Ying-Ching Shih ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/488

CPC classification number: H01L21/76885 ,  H01L21/486 ,  H01L21/56 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/181 ,  H05K1/0306 ,  H05K1/185 ,  H05K3/4007 ,  H05K2203/016 ,  H05K2203/025 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2224/16145 ,  H01L2924/00012

Abstract: A device includes an interposer, which includes a substrate; and at least one dielectric layer over the substrate. A plurality of through-substrate vias (TSVs) penetrate through the substrate. A first metal bump is in the at least one dielectric layer and electrically coupled to the plurality of TSVs. A second metal bump is over the at least one dielectric layer. A die is embedded in the at least one dielectric layer and bonded to the first metal bump.

Abstract translation: 一种装置包括：插入件，其包括基板; 以及衬底上的至少一个电介质层。 多个穿通基板通孔（TSV）穿透基板。 第一金属凸块在至少一个电介质层中并电耦合到多个TSV。 第二金属凸块在至少一个电介质层的上方。 模具嵌入在至少一个电介质层中并结合到第一金属凸块。

公开(公告)号：US20110304999A1

公开(公告)日：2011-12-15

申请号：US12834943

申请日：2010-07-13

Applicant: Chen-Hua Yu ,  Jing-Cheng Lin

Inventor： Chen-Hua Yu ,  Jing-Cheng Lin

IPC: H05K1/18 ,  H05K3/00 ,  H05K1/11

CPC classification number: H01L21/76898 ,  H01L23/13 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15321 ,  Y10T29/49124 ,  Y10T29/49165 ,  H01L2224/0401

Abstract: A device includes an interposer including a substrate, and a first through-substrate via (TSV) penetrating through the substrate. A glass substrate is bonded to the interposer through a fusion bonding. The glass substrate includes a second TSV therein and electrically coupled to the first TSV.

Abstract translation: 一种器件包括内插器，其包括衬底和穿透衬底的第一穿透衬底通孔（TSV）。 玻璃基板通过熔接结合到插入件上。 玻璃基板在其中包括第二TSV并且电耦合到第一TSV。

公开(公告)号：US20110304042A1

公开(公告)日：2011-12-15

申请号：US12846260

申请日：2010-07-29

Applicant: Jing-Cheng Lin ,  Ya-Hsi Hwung ,  Hsin-Yu Chen ,  Po-Hao Tsai ,  Yan-Fu Lin ,  Cheng-Lin Huang ,  Fang Wen Tsai ,  Wen-Chih Chiou

Inventor： Jing-Cheng Lin ,  Ya-Hsi Hwung ,  Hsin-Yu Chen ,  Po-Hao Tsai ,  Yan-Fu Lin ,  Cheng-Lin Huang ,  Fang Wen Tsai ,  Wen-Chih Chiou

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L23/488 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05099 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/1182 ,  H01L2224/11823 ,  H01L2224/1191 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13578 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/1369 ,  H01L2224/16058 ,  H01L2224/16148 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/16145 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A work piece includes a copper bump having a top surface and sidewalls. A protection layer is formed on the sidewalls, and not on the top surface, of the copper bump. The protection layer includes a compound of copper and a polymer, and is a dielectric layer.

Abstract translation: 工件包括具有顶表面和侧壁的铜凸块。 在铜凸块的侧壁而不是顶表面上形成保护层。 保护层包括铜和聚合物的化合物，并且是介电层。