公开(公告)号：US08481420B2

公开(公告)日：2013-07-09

申请号：US13048859

申请日：2011-03-15

申请人： Jong-Woo Ha ,  DaeSik Choi ,  Byoung Wook Jang

发明人： Jong-Woo Ha ,  DaeSik Choi ,  Byoung Wook Jang

IPC分类号： H01L21/44 ,  H01L21/48

CPC分类号： H01L23/3128 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/49541 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/03 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit die having an active side and a passive side; providing a contact pad having a top side oriented in a same direction as the passive side; connecting an inner bond wire to the contact pad and the integrated circuit die; and molding a stacking structure around the contact pad, the inner bond wire, and the integrated circuit die with the passive side and the top side exposed, and the stacking structure having a top structure surface on top and adjacent to or below the integrated circuit die, and a horizontal member under the integrated circuit die and forming a cavity.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供具有有源侧和被动侧的集成电路管芯; 提供具有朝向与被动侧相同方向的顶面的接触垫; 将内部接合线连接到接触焊盘和集成电路管芯; 以及在所述接触焊盘，所述内部接合线和所述集成电路管芯周围形成堆叠结构，其中所述被动侧和所述顶侧暴露，并且所述堆叠结构具有位于所述集成电路模具的顶部并且靠近所述集成电路模具的顶部结构表面 ，以及集成电路模具下方的水平构件，并形成空腔。

公开(公告)号：US08476115B2

公开(公告)日：2013-07-02

申请号：US13100235

申请日：2011-05-03

申请人： DaeSik Choi ,  Sang Mi Park ,  KyungHoon Lee

发明人： DaeSik Choi ,  Sang Mi Park ,  KyungHoon Lee

IPC分类号： H01L21/60

CPC分类号： H01L21/56 ,  H01L21/50 ,  H01L23/10 ,  H01L23/34 ,  H01L23/36 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/92225 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/07811 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device has an interposer with a die attach area interior to the interposer and cover attach area outside the die attach area. A channel is formed into a surface of the interposer within the cover attach area. A dam material is formed over the surface of the interposer within the cover attach area between the channel and edge of the interposer. A semiconductor die is mounted to the die attach area of the interposer. An adhesive material is deposited in the cover attach area away from the channel and dam material. A cover, such as a heat spreader or shielding layer, is mounted to the die and interposer within the cover attach area. The cover presses the adhesive material into the channel and against the dam material to control outward flow of the adhesive material. Alternatively, ACF can be formed over the interposer to mount the cover.

摘要翻译： 半导体器件具有插入件，其内部具有管芯附着区域，并且在管芯附着区域外部具有覆盖附着区域。 通道形成在盖附接区域内的插入件的表面中。 在插入器的通道和边缘之间的覆盖附着区域内的中介层的表面上形成坝体材料。 将半导体管芯安装到插入件的管芯附着区域。 粘合剂材料沉积在覆盖物附着区域中，远离通道和坝体材料。 诸如散热器或屏蔽层的盖子被安装到盖子附接区域内的模具和插入件上。 盖子将粘合剂材料压入通道并抵靠坝体材料以控制粘合剂材料的向外流动。 或者，ACF可以形成在插入件上方以安装盖。

公开(公告)号：US20130113118A1

公开(公告)日：2013-05-09

申请号：US13289811

申请日：2011-11-04

申请人： MinJung Kim ,  JoungIn Yang ,  DaeSik Choi ,  KyungEun Kim

发明人： MinJung Kim ,  JoungIn Yang ,  DaeSik Choi ,  KyungEun Kim

IPC分类号： H01L23/48 ,  H01L21/58

CPC分类号： H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/8159 ,  H01L2224/816 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/81805

摘要： A semiconductor device has a semiconductor die with bumps formed over a surface of the semiconductor die. A conductive layer is formed over a substrate. A patterning layer is formed over the substrate and conductive layer. A masking layer having an opaque portion and linear gradient contrast portion is formed over the patterning layer. The linear gradient contrast portion transitions from near transparent to near opaque. The patterning layer is exposed to ultraviolet light through the masking layer. The masking layer is removed and a portion of the patterning layer is removed to form an opening having a sloped surface to expose the conductive layer. The sloped surface in patterning layer can be formed by laser direct ablation. The semiconductor die is mounted to the substrate with the bumps electrically connected to the conductive layer and physically separated from the patterning layer.

摘要翻译： 半导体器件具有形成在半导体管芯的表面上的凸起的半导体管芯。 在衬底上形成导电层。 在衬底和导电层上形成图形层。 在图案化层上形成具有不透明部分和线性梯度对比部分的掩模层。 线性梯度对比部分从近透明转变为近似不透明。 图案化层通过掩模层暴露于紫外光。 去除掩模层，去除图形层的一部分以形成具有倾斜表面的开口以暴露导电层。 图案化层中的倾斜表面可以通过激光直接烧蚀形成。 将半导体管芯安装到基板上，凸块与导电层电连接并与图形层物理分离。

公开(公告)号：US20130105963A1

公开(公告)日：2013-05-02

申请号：US13287035

申请日：2011-11-01

申请人： DaeSik Choi ,  JoungIn Yang ,  MinJung Kim ,  Sang Mi Park ,  MinWook Yu

发明人： DaeSik Choi ,  JoungIn Yang ,  MinJung Kim ,  Sang Mi Park ,  MinWook Yu

IPC分类号： H01L23/34 ,  H01L21/50

CPC分类号： H01L21/6835 ,  H01L23/36 ,  H01L23/42 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L29/0657 ,  H01L2221/68345 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/29007 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/8485 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10158 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/01082 ,  H01L2224/11 ,  H01L2924/0665 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2224/32057 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2224/81805

摘要： A semiconductor device has a semiconductor die mounted to a substrate. A recess is formed in a back surface of the semiconductor die to an edge of the semiconductor die with sidewalls on at least two sides of the semiconductor die. The sidewalls are formed by removing a portion of the back surface of the die, or by forming a barrier layer on at least two sides of the die. A channel can be formed in the back surface of the semiconductor die to contain the TIM. A TIM is formed in the recess. A heat spreader is mounted in the recess over the TIM with a down leg portion of the heat spreader thermally connected to the substrate. The sidewalls contain the TIM to maintain uniform coverage of the TIM between the heat spreader and back surface of the semiconductor die.

摘要翻译： 半导体器件具有安装到衬底的半导体管芯。 在半导体管芯的后表面中形成有在半导体管芯的至少两侧具有侧壁的半导体管芯的边缘的凹部。 通过去除模具的后表面的一部分，或者通过在模具的至少两侧上形成阻挡层来形成侧壁。 可以在半导体管芯的后表面中形成通道以容纳TIM。 在凹部中形成有TIM。 散热器安装在TIM上的凹部中，散热器的下脚部分热连接到基板。 侧壁包含TIM以保持散热器和半导体管芯的后表面之间的TIM的均匀覆盖。

公开(公告)号：US08409921B2

公开(公告)日：2013-04-02

申请号：US12834176

申请日：2010-07-12

申请人： Heap Hoe Kuan ,  Hamid Eslampour ,  DaeSik Choi ,  Rui Huang ,  Taeg Ki Lim

发明人： Heap Hoe Kuan ,  Hamid Eslampour ,  DaeSik Choi ,  Rui Huang ,  Taeg Ki Lim

IPC分类号： H01L23/02

CPC分类号： H01L21/565 ,  H01L21/561 ,  H01L23/562 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/3511

摘要： A method of manufacture of an integrated circuit package system includes: providing a substrate with a top surface; configuring the top surface to include electrical contacts and an integrated circuit; providing a structure over the substrate with only a honeycomb meshwork of posts contacting the top surface of the substrate; and depositing a material to prevent warpage of the substrate on the top surface of the substrate and over the integrated circuit, the material patterned to have discrete hollow conduits that expose the electrical contacts.

摘要翻译： 集成电路封装系统的制造方法包括：向基板提供顶表面; 配置顶表面以包括电触头和集成电路; 在衬底上提供仅具有接触衬底的顶表面的柱的蜂窝状网状结构; 以及沉积材料以防止衬底在衬底的顶表面上以及集成电路上的翘曲，该图案化的材料具有暴露电接触的分立的中空导管。

公开(公告)号：US20130037936A1

公开(公告)日：2013-02-14

申请号：US13208027

申请日：2011-08-11

申请人： DaeSik Choi ,  YeongIm Park ,  HyungMin Lee

发明人： DaeSik Choi ,  YeongIm Park ,  HyungMin Lee

IPC分类号： H01L21/50 ,  H01L23/498 ,  H01L21/56

CPC分类号： H01L21/565 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/01082 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a substrate and first semiconductor die to the substrate. A plurality of vertically-oriented discrete electrical devices, such as a capacitor, inductor, resistor, diode, or transistor, is mounted over the substrate in proximity to the first semiconductor die. A first terminal of the discrete electrical devices is connected to the substrate. A plurality of bumps is formed over the substrate adjacent to the discrete electrical devices. An encapsulant is deposited over and between the first semiconductor die and substrate. A portion of the bumps and a second terminal of the discrete electrical devices is exposed from the encapsulant. An interconnect structure is formed over a surface of the substrate opposite the first semiconductor die. The semiconductor devices are stackable and electrically connected through the substrate, discrete electrical devices, and bumps. A heat spreader or second semiconductor die can be disposed between the stacked semiconductor devices.

摘要翻译： 半导体器件具有衬底和第一半导体管芯到衬底。 多个垂直取向的分立电气装置，例如电容器，电感器，电阻器，二极管或晶体管，安装在靠近第一半导体管芯的衬底上。 分立电气设备的第一端子连接到基板。 在与分立电气装置相邻的衬底上形成多个凸块。 密封剂沉积在第一半导体管芯和衬底之上和之间。 凸块的一部分和离散电气装置的第二端子从密封剂暴露出来。 在与第一半导体管芯相对的衬底的表面上形成互连结构。 半导体器件可堆叠并通过衬底电连接，分立的电子器件和凸块。 散热器或第二半导体管芯可以设置在堆叠的半导体器件之间。

公开(公告)号：US20120326291A1

公开(公告)日：2012-12-27

申请号：US13165658

申请日：2011-06-21

申请人： DaeSik Choi ,  Oh Han Kim ,  Jung SeIl

发明人： DaeSik Choi ,  Oh Han Kim ,  Jung SeIl

IPC分类号： H01L23/16 ,  H01L23/522 ,  H01L21/98 ,  H01L23/34

CPC分类号： H01L21/563 ,  H01L23/4334 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/15311

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a flip chip to the substrate; attaching a heat slug to the substrate and the flip chip; and forming a moldable underfill having a top underfill surface on the substrate, the flip chip, and the heat slug, the moldable underfill having a characteristic of being liquid at room temperature and the top underfill surface over the flip chip.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供基板; 将倒装芯片附接到基板; 将散热片附接到基板和倒装芯片; 并且在基板，倒装芯片和热芯块上形成具有顶部底部填充表面的可成型底部填充物，可模塑底部填充物具有在室温下为液体的特性，以及倒装芯片上的顶部底部填充表面。

公开(公告)号：US20120280374A1

公开(公告)日：2012-11-08

申请号：US13100235

申请日：2011-05-03

申请人： DaeSik Choi ,  Sang Mi Park ,  KyungHoon Lee

发明人： DaeSik Choi ,  Sang Mi Park ,  KyungHoon Lee

IPC分类号： H01L23/552 ,  H01L23/48 ,  H01L21/60 ,  H01L21/50

CPC分类号： H01L21/56 ,  H01L21/50 ,  H01L23/10 ,  H01L23/34 ,  H01L23/36 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/92225 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/07811 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device has an interposer with a die attach area interior to the interposer and cover attach area outside the die attach area. A channel is formed into a surface of the interposer within the cover attach area. A dam material is formed over the surface of the interposer within the cover attach area between the channel and edge of the interposer. A semiconductor die is mounted to the die attach area of the interposer. An adhesive material is deposited in the cover attach area away from the channel and dam material. A cover, such as a heat spreader or shielding layer, is mounted to the die and interposer within the cover attach area. The cover presses the adhesive material into the channel and against the dam material to control outward flow of the adhesive material. Alternatively, ACF can be formed over the interposer to mount the cover.

摘要翻译： 半导体器件具有插入件，其内部具有管芯附着区域，并且在管芯附着区域外部具有覆盖附着区域。 通道形成在盖附接区域内的插入件的表面中。 在插入器的通道和边缘之间的覆盖附着区域内的中介层的表面上形成坝体材料。 将半导体管芯安装到插入件的管芯附着区域。 粘合剂材料沉积在覆盖物附着区域中，远离通道和坝体材料。 诸如散热器或屏蔽层的盖子被安装到盖子附接区域内的模具和插入件上。 盖子将粘合剂材料压入通道并抵靠坝体材料以控制粘合剂材料的向外流动。 或者，ACF可以形成在插入件上方以安装盖。

公开(公告)号：US20120241979A1

公开(公告)日：2012-09-27

申请号：US13052590

申请日：2011-03-21

申请人： DaeSik Choi ,  Jong-Woo Ha ,  Seung Won Kim

发明人： DaeSik Choi ,  Jong-Woo Ha ,  Seung Won Kim

IPC分类号： H01L23/49 ,  H01L21/50

CPC分类号： H01L23/3135 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06155 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/45565 ,  H01L2224/45599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8314 ,  H01L2224/8592 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a substrate; connecting an integrated circuit die to the substrate, with the integrated circuit die having peripheral sides; molding a step mold covering one of the peripheral sides; attaching an intermediate die directly over the integrated circuit die, offset to one of the peripheral sides adjacent to the step mold; and directly connecting the intermediate die to the substrate.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供基板; 将集成电路管芯连接到衬底，集成电路管芯具有周边; 模制覆盖一个周边的阶梯模; 将中间模直接连接在集成电路模具上，偏移到与步进模具相邻的周边之一; 并将中间管芯直接连接到基板。

公开(公告)号：US08189344B2

公开(公告)日：2012-05-29

申请号：US12136037

申请日：2008-06-09

申请人： Sang-Ho Lee ,  Soo-San Park ,  DaeSik Choi

发明人： Sang-Ho Lee ,  Soo-San Park ,  DaeSik Choi

IPC分类号： H01L23/02 ,  H01L21/00 ,  H05K1/16

CPC分类号： H01L23/3128 ,  H01L23/3135 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L24/91 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04073 ,  H01L2224/1134 ,  H01L2224/1308 ,  H01L2224/13099 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48475 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85951 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An integrated circuit package system includes: providing a package substrate; mounting an interposer chip containing active circuitry over the package substrate; attaching a conductive bump stack having a base bump end and a stud bump end, the base bump end on the interposer chip; connecting a stack connector to the interposer chip and the package substrate; and applying a package encapsulant over the interposer chip, the stack connector, and the conductive bump stack with the stud bump end of the conductive bump stack substantially exposed.

摘要翻译： 集成电路封装系统包括：提供封装衬底; 将包含有源电路的插入器芯片安装在所述封装衬底上; 附接具有基底凸起端和柱形凸起端的导电凸块，所述基座凸起端在所述插入片上; 将堆叠连接器连接到插入器芯片和封装衬底; 以及将封装密封剂施加在所述插入器芯片，所述堆叠连接器以及所述导电凸块堆叠上，其中所述导电凸块的所述凸块的端部基本暴露。