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268 条记录 (耗时 0.029 秒)

    Spin-on cap layer, and semiconductor device containing same
    92.
    发明授权
    Spin-on cap layer, and semiconductor device containing same 有权
    旋转盖层，以及包含其的半导体器件

    公开(公告)号：US06724069B2

    公开(公告)日：2004-04-20

    申请号：US09827160

    申请日：2001-04-05

    申请人： Timothy Joseph Dalton ,  Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Christy Sensenich Tyberg

    发明人： Timothy Joseph Dalton ,  Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Christy Sensenich Tyberg

    IPC分类号： H01L2358

    CPC分类号： H01L21/76835 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A spin-on cap useful as a post-CMP cap for Cu interconnect structures is provided. The inventive spin-on cap includes a low-k dielectric (on the order of 3.5 or less) and at least one additive. The at least one additive employed in the present invention is capable of binding Cu ions, and is soluble in the spun-on low-k dielectric. The spin-on cap of the present invention may further include a spun-on low-k (on the order of 3.5 or less) reactive-ion etch (RIE) stop layer. Spin-on caps containing a bilayer of low-dielectric plus at least additive and low-k RIE stop layer are preferred. It is noted that the inventive spin-on cap of the present invention does not significantly increase the effective dielectric constant of the interconnect structure and does not add additional cost to the fabrication of the interconnect structure since a single deposition tool, i.e., spin coating tool, is employed. Moreover, because of the presence of the additive in the spin-on cap, Cu migration is substantially minimized.

    摘要翻译： 提供了一种用作Cu互连结构的CMP后盖的旋涂帽。 本发明的旋涂帽包括低k电介质（约3.5或更小）和至少一种添加剂。 本发明中使用的至少一种添加剂能够结合Cu离子，并且可溶于旋转的低k电介质。 本发明的旋涂帽还可以包括旋转低k（约3.5或更小）反应离子蚀刻（RIE）停止层。 包含低电介质加上至少添加和低k RIE停止层的双层的旋转盖是优选的。 注意，本发明的本发明的旋涂帽不会显着增加互连结构的有效介电常数，并且不会增加互连结构的制造的额外成本，因为单个沉积工具，即旋涂工具 ，被雇用。 此外，由于在旋涂帽中存在添加剂，所以Cu迁移基本上被最小化。

    Semiconductor recessed mask interconnect technology
    93.
    发明授权
    Semiconductor recessed mask interconnect technology 失效
    半导体凹陷掩模互连技术

    公开(公告)号：US06657305B1

    公开(公告)日：2003-12-02

    申请号：US09703734

    申请日：2000-11-01

    申请人： Stephen Alan Cohen ,  Timothy Joseph Dalton ,  John Anthony Fitzsimmons ,  Stephen McConnell Gates ,  Brian Wayne Herbst ,  Sampath Purushothaman ,  Stanley Joseph Whitehair

    发明人： Stephen Alan Cohen ,  Timothy Joseph Dalton ,  John Anthony Fitzsimmons ,  Stephen McConnell Gates ,  Brian Wayne Herbst ,  Sampath Purushothaman ,  Stanley Joseph Whitehair

    IPC分类号： H01L2348

    CPC分类号： H01L21/76829 ,  H01L21/76804 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A metal plus low dielectric constant (low-k) interconnect structure is provided for a semiconductor device wherein adjacent regions in a surface separated by a dielectric have dimensions in width and spacing in the sub 250 nanometer range, and in which reduced lateral leakage current between adjacent metal lines, and a lower effective dielectric constant than a conventional structure, is achieved by the positioning of a differentiating or mask member that is applied for the protection of the dielectric in subsequent processing operations, at a position about 2-5 nanometers below a, to be planarized, surface where there will be a lower electric field. The invention is particularly useful in the damascene type device structure in the art wherein adjacent conductors extend from a substrate through an interlevel dielectric material, connections are made in a trench, a diffusion barrier liner is provided in the interlevel dielectric material and masking is employed to protect the dielectric material between conductors during processing operations.

    摘要翻译： 为半导体器件提供金属加上低介电常数（低k）互连结构，其中由电介质隔开的表面中的相邻区域在亚250纳米范围内具有宽度和间距的尺寸，并且其中减小横向漏电流 相邻的金属线和比常规结构更低的有效介电常数是通过在后续处理操作中在约2-5纳米以下的位置处定位用于保护电介质的微分或掩模构件来实现的 ，要平坦化，会有较低电场的表面。 本发明特别适用于本领域的镶嵌型器件结构，其中相邻导体从衬底延伸通过层间电介质材料，在沟槽中形成连接，在层间电介质材料中提供扩散阻挡衬垫，并且使用掩模 在处理操作期间保护导体之间的电介质材料。

    Metal embedded passivation layer structure for microelectronic interconnect formation, customization and repair
    95.
    发明授权
    Metal embedded passivation layer structure for microelectronic interconnect formation, customization and repair 失效
    金属嵌入式钝化层结构，用于微电子互连形成，定制和修复

    公开(公告)号：US06255671B1

    公开(公告)日：2001-07-03

    申请号：US09002840

    申请日：1998-01-05

    申请人： Nestor Alexander Bojarczuk, Jr. ,  Supratik Guha ,  Arunava Gupta ,  Sampath Purushothaman

    发明人： Nestor Alexander Bojarczuk, Jr. ,  Supratik Guha ,  Arunava Gupta ,  Sampath Purushothaman

    IPC分类号： H01L3300

    CPC分类号： H01L21/76894 ,  H01L21/76823 ,  H01L21/76838 ,  H01L23/5254 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A structure includes a metal nitride film of the form MN, where M is selected from the group consisting of Ga, In, AlGa, AlIn, and AlGaIn. The structure has at least one electrically conductive metal region that is formed within and from the metal nitride film by a thermal process driven by absorption of light having a predetermined wavelength. Single films comprised of AlN are also within the scope of this invention, wherein an Al trace or interconnect is formed by laser radiation of wavelength 248 nm so as to contact circuitry that exists under the film. Multilayered stacks of films are also within the scope of the teachings of this invention. In this case each film layer may be separately deposited and then illuminated to selectively form the desired electrical connection(s), which may also connect to conductive feature(s) in an underlying layer, or a plurality of metal nitride layers are stacked bottom to top in order of increasing electronic band gap energy value, and then the conductive features are written into selective ones of the layers by controlling the wavelength of the light to be absorbed in a desired layer. The teachings of this invention can be employed to fabricate fuses and anti-fuses enabling selective circuit customization, test and repair. Also disclosed is a technique for forming electrical resistors in a metal nitride layer by adjusting the electrical resistance of the metallization formed from the metal nitride film layer.

    摘要翻译： 结构包括形式为MN的金属氮化物膜，其中M选自Ga，In，AlGa，AlIn和AlGaIn。 该结构具有通过由具有预定波长的光吸收驱动的热处理而形成在金属氮化物膜内和从金属氮化物膜形成的至少一个导电金属区域。 由AlN组成的单个膜也在本发明的范围内，其中通过波长为248nm的激光辐射形成Al迹线或互连，以便接触存在于膜下面的电路。 多层薄膜也在本发明的教导的范围内。 在这种情况下，每个膜层可以被分开沉积，然后照亮以选择性地形成所需的电连接，其也可以连接到下层中的导电特征，或者多个金属氮化物层被堆叠到底部 顶部按照增加电子带隙能量值的顺序，然后通过控制要在所需层中吸收的光的波长将导电特征写入选择层中。 本发明的教导可用于制造保险丝和抗熔丝，从而能够进行选择性电路定制，测试和修理。 还公开了通过调整由金属氮化物膜层形成的金属化层的电阻来形成金属氮化物层中的电阻器的技术。