公开(公告)号：US07211470B2

公开(公告)日：2007-05-01

申请号：US11216133

申请日：2005-09-01

申请人： Norman A. Card ,  John M. Lauffer

发明人： Norman A. Card ,  John M. Lauffer

IPC分类号： H01L21/00

CPC分类号： H01L21/67126 ,  H01L21/486 ,  H05K3/4053 ,  H05K3/4069 ,  H05K2201/0116 ,  H05K2201/0959 ,  H05K2203/0139 ,  H05K2203/082 ,  H05K2203/1476

摘要： A method and apparatus for depositing conductive paste in openings of a circuitized substrate such as a multilayered printed circuit board to produce effective conductive thru-holes capable of being electrically coupled to selected conductive layers of the substrate. The invention comprises using vacuum to draw from the underside of the substrate while substantially simultaneously applying the paste onto the substrate's opposing surface. One example of means for accomplishing such paste application is a squeegee, and in one embodiment, two such squeegees may be used. A porous member is used to engage the substrate's undersurface during the vacuum draw, this member being positioned atop a base vacuum member through which the vacuum is drawn.

摘要翻译： 一种用于在诸如多层印刷电路板的电路化基板的开口中沉积导电浆料以产生能够电耦合到所述基板的选定导电层的有效导电通孔的方法和装置。 本发明包括使用真空从衬底的下侧抽出，同时基本上同时将糊料施加到衬底的相对表面上。 用于实现这种糊剂应用的手段的一个实例是刮刀，并且在一个实施例中，可以使用两个这样的刮板。 在真空拉伸期间，使用多孔构件与基板的下表面接合，该构件位于真空抽出的底部真空构件的顶部。

公开(公告)号：US07211289B2

公开(公告)日：2007-05-01

申请号：US10737974

申请日：2003-12-18

申请人： James M. Larnerd ,  John M. Lauffer ,  Voya R. Markovich ,  Kostas I. Papathomas

发明人： James M. Larnerd ,  John M. Lauffer ,  Voya R. Markovich ,  Kostas I. Papathomas

IPC分类号： B05D5/12 ,  B28B19/00 ,  B29B15/10

CPC分类号： H05K3/429 ,  H01L2224/13 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/421 ,  H05K2201/0347 ,  H05K2201/09454 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/0969 ,  H05K2201/09845

摘要： A method of making a printed circuit board in which conductive thru-holes are formed within two dielectric layers of the board's structure so as to connect designated conductive layers. One hole connects two adjacent layers and the other connects two adjacent layers, including one of the conductive layers connected by the other hole. It is also possible to connect all three conductive layers using one or more holes. The resulting holes may be filled, e.g., with metal plating, or conductive or non-conductive paste. In the case of the latter, it is also possible to provide a top covering conductive layer over the paste, e.g., to serve as a pad or the like on the board's external surface.

摘要翻译： 一种制造印刷电路板的方法，其中导电通孔形成在板结构的两个电介质层内，以便连接指定的导电层。 一个孔连接两个相邻的层，另一个连接两个相邻的层，包括通过另一个孔连接的一个导电层。 也可以使用一个或多个孔连接所有三个导电层。 所得到的孔可以例如用金属电镀或导电或不导电的糊料填充。 在后者的情况下，也可以在浆料上方设置顶部覆盖导电层，例如在板的外表面上用作衬垫等。

公开(公告)号：US20070089290A1

公开(公告)日：2007-04-26

申请号：US11634287

申请日：2006-12-06

申请人： John Lauffer ,  Voya Markovich ,  James McNamara ,  David Thomas

发明人： John Lauffer ,  Voya Markovich ,  James McNamara ,  David Thomas

IPC分类号： H05K3/36 ,  H05K3/20

CPC分类号： H05K1/0216 ,  H05K1/0228 ,  H05K2201/09236 ,  H05K2201/09672 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method of making a printed circuit board in which the board includes a common power plane having dielectric layers on opposing sides thereof and a signal layer on each of said dielectric layers, each signal layer comprising a plurality of substantially parallel signal lines running in substantially similar directions across said signal layers. Predetermined portions of the signal lines in one signal layer are aligned relative to and also parallel to corresponding signal lines in the other signal layer, with the power plane being located between these portions. Through hole connections are provided between selected signal lines in the two layers, these occurring through clearance holes in the power plane so as to be isolated therefrom.

摘要翻译： 一种制造印刷电路板的方法，其中所述基板包括在其相对侧上具有电介质层的公共电源平面和每个所述电介质层上的信号层，每个信号层包括基本相似的多条基本上平行的信号线 跨越所述信号层的方向。 一个信号层中的信号线的预定部分相对于并且平行于另一个信号层中的相应的信号线，而功率平面位于这些部分之间。 在两层中的选定信号线之间提供通孔连接，这些连接通过电源平面中的间隙而发生，从而与其隔离。

公开(公告)号：US07209368B2

公开(公告)日：2007-04-24

申请号：US10790747

申请日：2004-03-03

申请人： John M. Lauffer ,  Voya Markovich ,  Corey Seastrand ,  David L. Thomas

发明人： John M. Lauffer ,  Voya Markovich ,  Corey Seastrand ,  David L. Thomas

IPC分类号： H05K9/00

CPC分类号： H01L23/552 ,  H01L23/3128 ,  H01L23/5383 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0219 ,  H05K1/024 ,  H05K1/113 ,  H05K3/4623 ,  H05K3/4688 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/061 ,  H01L2224/05599

摘要： A circuitized substrate in which at least one signal line used therein is shielded by a pair of opposingly positioned ground lines which in turn are electrically coupled to a ground plane located beneath the signal and ground lines and separated therefrom by a common interim dielectric layer. An electrical assembly including the circuitized substrate as part thereof and a method of making the circuitized substrate are also included. The substrate may form part of a larger structure such as a PCB, chip carrier or the like.

摘要翻译： 其中其中使用的至少一个信号线被一对相对定位的接地线屏蔽的电路化基板，所述接地线又电耦合到位于信号和接地线下方的接地平面，并通过共同的中间介质层与其分离。 包括作为其一部分的电路化基板的电气组件和制造电路化基板的方法也包括在内。 衬底可以形成较大结构的一部分，例如PCB，芯片载体等。

公开(公告)号：US07176383B2

公开(公告)日：2007-02-13

申请号：US10740398

申请日：2003-12-22

申请人： John M. Lauffer ,  Voya R. Markovich ,  James J. McNamara, Jr. ,  David L. Thomas

发明人： John M. Lauffer ,  Voya R. Markovich ,  James J. McNamara, Jr. ,  David L. Thomas

IPC分类号： H05K1/03

CPC分类号： H05K1/0216 ,  H05K1/0228 ,  H05K2201/09236 ,  H05K2201/09672 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A printed circuit board and a method of making same in which the board includes a common power plane having dielectric layers on opposing sides thereof and a signal layer on each of said dielectric layers, each signal layer comprising a plurality of substantially parallel signal lines running in substantially similar directions across said signal layers. Predetermined portions of the signal lines in one signal layer are aligned relative to and also parallel to corresponding signal lines in the other signal layer, with the power plane being located between these portions. Through hole connections are provided between selected signal lines in the two layers, these occurring through clearance holes in the power plane so as to be isolated therefrom.

摘要翻译： 一种印刷电路板及其制造方法，其中所述板包括在其相对侧上具有电介质层的公共电源平面和每个所述电介质层上的信号层，每个信号层包括多条基本上平行的信号线， 基本相似的方向跨越所述信号层。 一个信号层中的信号线的预定部分相对于并且平行于另一个信号层中的相应的信号线，而功率平面位于这些部分之间。 在两层中的选定信号线之间提供通孔连接，这些连接通过电源平面中的间隙而发生，从而与其隔离。

公开(公告)号：US07169313B2

公开(公告)日：2007-01-30

申请号：US11128272

申请日：2005-05-13

申请人： Norman A. Card ,  Robert D. Edwards ,  John J. Konrad ,  Roy H. Magnuson ,  Timothy L. Wells ,  Michael Wozniak

发明人： Norman A. Card ,  Robert D. Edwards ,  John J. Konrad ,  Roy H. Magnuson ,  Timothy L. Wells ,  Michael Wozniak

IPC分类号： H01B13/00 ,  H01K3/10

CPC分类号： H05K3/427 ,  H05K3/108 ,  H05K3/382 ,  H05K3/429 ,  H05K2203/0353 ,  H05K2203/1476 ,  Y10T29/49156 ,  Y10T29/49165

摘要： A method of plating a circuit pattern on a substrate to produce a circuitized substrate (e.g., a printed circuit board) in which a dual step metallurgy application process is used in combination with a dual step photo-resist removal process. Thru-holes are also possible, albeit not required.

摘要翻译： 将电路图案电镀在基板上以制造其中双步骤冶金施加工艺与双步骤光刻胶去除工艺结合使用的电路化基板（例如印刷电路板）的方法。 通孔也是可以的，尽管不是必需的。

公开(公告)号：US20070006452A1

公开(公告)日：2007-01-11

申请号：US11177413

申请日：2005-07-11

申请人： Frank Egitto ,  Voya Markovich ,  Luis Matienzo

发明人： Frank Egitto ,  Voya Markovich ,  Luis Matienzo

IPC分类号： B32B37/00 ,  H05K3/30

CPC分类号： H05K3/462 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/445 ,  H05K2201/015 ,  H05K2201/0245 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/1152 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T29/49165 ,  Y10T156/1056 ,  Y10T156/1062

摘要： A method of making a circuitized substrate which includes a high temperature dielectric material in combination with a low temperature conductive paste, the paste including an organic binder component and at least one metallic component. The flakes of the metallic component are sintered to form a conductive path through the dielectric when the dielectric is used as a layer in the substrate.

摘要翻译： 一种制造电路化基板的方法，该基板包括与低温导电浆料组合的高温电介质材料，所述糊料包括有机粘合剂成分和至少一种金属成分。 当电介质用作衬底中的层时，金属部件的薄片被烧结以形成通过电介质的导电路径。

公开(公告)号：US07157647B2

公开(公告)日：2007-01-02

申请号：US10882170

申请日：2004-07-02

申请人： John M. Lauffer ,  James M. Larnerd ,  Voya R. Markovich

发明人： John M. Lauffer ,  James M. Larnerd ,  Voya R. Markovich

IPC分类号： H05K1/11

CPC分类号： H05K3/44 ,  H05K1/056 ,  H05K3/0047 ,  H05K3/0052 ,  H05K3/429 ,  H05K3/4641 ,  H05K2203/0323 ,  H05K2203/1476 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155

摘要： A circuitized substrate which includes a plurality of contiguous open segments along a side edge portion of the at least one electrically conductive layer thereof, these open segments isolated by a barrier of dielectric material which substantially fills the open segments, e.g., during a lamination process which bonds two dielectric layers of the substrate to the conductive layer. A method of making the substrate, an electrical assembly utilizing the substrate, a multilayered circuitized assembly also utilizing the substrate and an information handling system, e.g., a mainframe computer, are also provided.

摘要翻译： 电路化衬底，其包括沿其至少一个导电层的侧边缘部分的多个邻接的开放段，这些开放段通过电介质材料的屏障隔离，所述阻挡层基本上填充开放段，例如在层压过程期间 将基板的两个电介质层粘合到导电层。 还提供了制造衬底的方法，利用衬底的电组件，还利用衬底的多层电路化组件和诸如主机的信息处理系统。

公开(公告)号：US20060274891A1

公开(公告)日：2006-12-07

申请号：US11141494

申请日：2005-06-01

申请人： Ashwinkumar Bhatt ,  Varaprasad Calmidi ,  James McNamara ,  Sanjeev Sathe

发明人： Ashwinkumar Bhatt ,  Varaprasad Calmidi ,  James McNamara ,  Sanjeev Sathe

IPC分类号： H01J35/10 ,  H01J35/12

CPC分类号： G01N23/046 ,  G01N2223/3103 ,  G01N2223/419 ,  G01N2223/643 ,  H01J2235/1262

摘要： An imaging inspection apparatus which utilizes a plurality of individual imaging devices (e.g., X-ray Computer Tomography scanning devices) positioned on a frame for directing beams onto articles having objects therein to detect the objects based on established criteria. The apparatus utilizes a cooling structure to provide cooling to the imaging devices.

摘要翻译： 一种成像检查装置，其利用位于框架上的多个单独的成像装置（例如，X射线计算机断层摄影扫描装置），用于将光束引导到具有其中的物体的物品上，以根据建立的标准检测物体。 该装置利用冷却结构为成像装置提供冷却。

公开(公告)号：US20060240594A1

公开(公告)日：2006-10-26

申请号：US11455183

申请日：2006-06-19

申请人： Lawrence Fraley ,  Voya Markovich

发明人： Lawrence Fraley ,  Voya Markovich

IPC分类号： H01L21/00

CPC分类号： H01L23/145 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5383 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/024 ,  H05K1/113 ,  H05K3/4623 ,  H05K3/4688 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/061 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of making a multi-chip electronic package which utilizes an organic, laminate chip carrier and a pair of semiconductor chips positioned on an upper surface of the carrier in a stacked orientation. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples one or both of the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities. The first chip, e.g., an ASIC chip, is solder bonded to the carrier while the second chip, e.g., a memory chip, is secured to the first chip's upper surface and coupled to the carrier using a plurality of wirebond connections.

摘要翻译： 一种制造多芯片电子封装的方法，该多芯片电子封装利用有机层压芯片载体和位于载体的上表面上的堆叠取向的一对半导体芯片。 有机层压芯片载体由多个导电平面和电介质层组成，并将芯片中的一个或两个耦合到其底表面上的下面的导体。 载体可以包括高速部分，以确保半导体芯片之间的高频连接，并且还可以包括用于增强操作能力的内部电容器和/或导热构件。 第一芯片（例如ASIC芯片）被焊接到载体上，而第二芯片（例如存储器芯片）被固定到第一芯片的上表面并且使用多个引线键合连接到载体。