公开(公告)号：US09711359B2

公开(公告)日：2017-07-18

申请号：US14826088

申请日：2015-08-13

Applicant: Lam Research Corporation

Inventor： Tom A. Kamp ,  Rodolfo P. Belen, Jr.

IPC: H01L21/302 ,  H01L21/461 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/033 ,  H01L21/311 ,  H01L21/027 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L21/0338 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144

Abstract: A method for etching an etch layer in a stack over a substrate wherein the etch layer is under a mask layer which is under a patterned organic mask is provided. The stack and substrate is placed on a support in the plasma chamber. A silicon based layer is deposited in situ over the stack. The silicon based layer is etched to form silicon based sidewalls or spacers on sides of the patterned organic mask. The mask layer is selectively etched with respect to the silicon based sidewalls or spacers, wherein the selectively etching the mask layer undercuts the silicon based sidewalls or spacers. The etch layer is selectively etched with respect to the mask layer. The stack and substrate are removed from the support and the plasma chamber.

公开(公告)号：US09706634B2

公开(公告)日：2017-07-11

申请号：US14970738

申请日：2015-12-16

Applicant: Varian Semiconductor Equipment Associates, Inc.

Inventor： Shurong Liang ,  Costel Biloiu ,  Glen F. R. Gilchrist ,  Vikram Singh ,  Christopher Campbell ,  Richard Hertel ,  Alexander Kontos ,  Piero Sferlazzo ,  Tsung-Liang Chen

IPC: H01H1/24 ,  H05H1/24 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/66

CPC classification number: H05H1/24 ,  H01J37/32009 ,  H01J37/32357 ,  H01J37/3244 ,  H01J37/32834 ,  H01J2237/327 ,  H01L21/3065 ,  H01L21/308 ,  H01L22/12 ,  H01L22/20

Abstract: An apparatus to treat a substrate. The apparatus may include a reactive gas source having a reactive gas outlet disposed in a process chamber, the reactive gas outlet to direct a first reactive gas to the substrate; a plasma chamber coupled to the process chamber and including an extraction plate having an extraction aperture extending along a first direction, disposed within the process chamber and movable along a second direction perpendicular to the first direction between a first position facing the reactive gas source and a second position facing the extraction aperture; and a gas flow restrictor disposed between the reactive gas outlet and the extraction aperture, the gas flow restrictor defining a differential pumping channel between at least the plasma chamber and substrate stage.

公开(公告)号：US09704765B2

公开(公告)日：2017-07-11

申请号：US14814703

申请日：2015-07-31

Applicant: Polar Semiconductor, LLC

Inventor： Peter N. Manos, II

IPC: H01L29/10 ,  H01L21/66 ,  H01L29/78 ,  H01L29/04 ,  H01L29/16 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/265 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L22/26 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/26513 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/78 ,  H01L22/12 ,  H01L27/0922 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/16 ,  H01L29/36 ,  H01L29/66681 ,  H01L29/7816

Abstract: A method of controlling an etch-pattern density of a polysilicon layer includes depositing polysilicon on a wafer. The method includes determining polysilicon-etch regions that include DMOS source regions within circuit-device areas of the wafer. The method includes calculating an etch area of the polysilicon-etch regions and then comparing the calculated etch area of the polysilicon-etch regions to a predetermined minimum etch area. If the calculated etch area is less than a predetermined threshold, the method adds polysilicon-etch regions within non-circuit-device areas to the determined polysilicon-etch regions within the circuit-device areas until the comparing step results in the calculated etch area of the polysilicon-etch regions being greater than the predetermined minimum etch area. The method includes etching the polysilicon from the polysilicon-etch regions in both the circuit-device areas and the non-circuit-device areas. Adding polysilicon-etch regions in non-circuit device areas can advantageously facilitate automatic process control of an etch step.

公开(公告)号：US20170194462A1

公开(公告)日：2017-07-06

申请号：US15463972

申请日：2017-03-20

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/02645 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/1037 ,  H01L29/161 ,  H01L29/36 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate, forming at least one precursor semiconductor fin from the semiconductor substrate, etching through at least a portion of the at least one precursor semiconductor fin to form at least one patterned precursor semiconductor fin having a gap therein. The at least one patterned precursor semiconductor fin includes a first vertical surface and a second vertical surface with the gap therebetween. In addition, the method further includes forming a semiconductor material in the gap of the at least one patterned precursor semiconductor fin, in which the first vertical surface and the second vertical surface laterally surround the semiconductor material, and transforming the at least one patterned precursor semiconductor fin into at least one semiconductor fin including the semiconductor material therein.

公开(公告)号：US20170194205A1

公开(公告)日：2017-07-06

申请号：US14979200

申请日：2015-12-22

Applicant: Infineon Technologies AG

Inventor： Gudrun Stranzl ,  Martin Zgaga ,  Markus Kahn ,  Guenter Denifl

IPC: H01L21/78 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/78 ,  H01L21/02115 ,  H01L21/0212 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/82 ,  H01L21/8258

Abstract: In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.

公开(公告)号：US09698024B2

公开(公告)日：2017-07-04

申请号：US14330092

申请日：2014-07-14

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Long-Shih Lin ,  Fu-Hsiung Yang ,  Kun-Ming Huang ,  Ming-Yi Lin ,  Paul Chu

IPC: H01L21/308 ,  H01L29/66 ,  H01L29/78 ,  H01L29/739 ,  G01R31/12 ,  H01L29/08 ,  G01R31/26 ,  H01L21/762

CPC classification number: H01L21/308 ,  G01R31/129 ,  G01R31/2637 ,  H01L21/3083 ,  H01L21/76275 ,  H01L21/76283 ,  H01L29/086 ,  H01L29/66325 ,  H01L29/66689 ,  H01L29/7394 ,  H01L29/7824

Abstract: Some embodiments of the present disclosure relate to a method to increase breakdown voltage of a power device. A power device is formed on a silicon-on-insulator (SOI) wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer. A recess is formed in a lower surface of the handle wafer to define a recessed region of the handle wafer. The recessed region of the handle wafer has a first handle wafer thickness, which is greater than zero. An un-recessed region of the handle wafer has a second handle wafer thickness, which is greater than the first handle wafer thickness. The first handle wafer thickness of the recessed region provides a breakdown voltage improvement for the power device.

公开(公告)号：US09696222B2

公开(公告)日：2017-07-04

申请号：US15231421

申请日：2016-08-08

Applicant: UCHICAGO ARGONNE, LLC

Inventor： Anirudha V. Sumant ,  Xinpeng Wang

IPC: H01L21/00 ,  G01L1/18 ,  H01L29/04 ,  H01L29/16 ,  H01L21/04 ,  H01L21/308 ,  G01B7/14 ,  H01L29/06 ,  H01L29/167 ,  G01B7/16

CPC classification number: G01L1/18 ,  B82Y10/00 ,  G01B7/14 ,  G01B7/18 ,  G01L1/2293 ,  H01L21/042 ,  H01L21/043 ,  H01L21/308 ,  H01L29/04 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/1602 ,  H01L29/167

Abstract: A UNCD nanowire comprises a first end electrically coupled to a first contact pad which is disposed on a substrate. A second end is electrically coupled to a second contact pad also disposed on the substrate. The UNCD nanowire is doped with a dopant and disposed over the substrate. The UNCD nanowire is movable between a first configuration in which no force is exerted on the UNCD nanowire and a second configuration in which the UNCD nanowire bends about the first end and the second end in response to a force. The UNCD nanowire has a first resistance in the first configuration and a second resistance in the second configuration which is different from the first resistance. The UNCD nanowire is structured to have a gauge factor of at least about 70, for example, in the range of about 70 to about 1,800.

公开(公告)号：US20170179291A1

公开(公告)日：2017-06-22

申请号：US15450201

申请日：2017-03-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Jing Lee ,  Chi-Wen Liu ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/778 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L29/161 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/157 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/432 ,  H01L29/66431 ,  H01L29/66712 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/7789 ,  H01L29/7802 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

Abstract: A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.

公开(公告)号：US20170154798A1

公开(公告)日：2017-06-01

申请号：US15318925

申请日：2014-09-19

Applicant: Mitsubishi Electric Corporation

Inventor： Nobuaki YAMANAKA ,  Daisuke CHIKAMORI ,  Shinichirou KATSUKI

IPC: H01L21/67 ,  H01L29/16 ,  H01L29/47 ,  C23F1/38 ,  H01L21/04

CPC classification number: H01L21/67086 ,  C23F1/38 ,  H01L21/0495 ,  H01L21/308 ,  H01L21/32134 ,  H01L29/1608 ,  H01L29/47

Abstract: A method for manufacturing a semiconductor device, includes: a preparation step, a flow step, and a processing step. The preparation step prepares an etching solution by dissolving titanium in an ammonia-hydrogen peroxide solution in advance before use of the ammonia-hydrogen peroxide solution for etching. The flow step flows the etching solution after the preparation step so that a concentration of the etching solution in a processing bath is constant. The processing step etches a metal film on a semiconductor wafer with the etching solution by putting in the processing bath the semiconductor wafer having a resist film and the metal film after the flow step is started. The metal film is preferably formed of titanium, and a temperature of the etching solution is preferably adjusted by flowing the etching solution so that the etching solution flows via a temperature controller.

公开(公告)号：US20170154775A1

公开(公告)日：2017-06-01

申请号：US15258144

申请日：2016-09-07

Applicant: International Business Machines Corporation

Inventor： KARTHIK BALAKRISHNAN ,  KANGGUO CHENG ,  POUYA HASHEMI ,  ALEXANDER REZNICEK

IPC: H01L21/02 ,  H01L21/3105 ,  H01L21/324 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L21/02694 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/28255 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/32055 ,  H01L21/324 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/7378 ,  H01L29/7848 ,  H01L29/785 ,  H01L31/1816 ,  H01L2924/10271

Abstract: A semiconductor device comprising a substrate having a region protruding from the substrate surface; a relaxed semiconductor disposed on the region; an additional semiconductor disposed on the relaxed semiconductor; and low density dielectric disposed next to and at least partially underneath the relaxed semiconductor and adjacent to the protruding region of the substrate.