公开(公告)号：US20130082372A1

公开(公告)日：2013-04-04

申请号：US13250606

申请日：2011-09-30

Applicant: Wen-Yi Lin ,  Ming-Chih Yew ,  Po-Yao Lin ,  Jing Ruei Lu ,  Jiun Yi Wu

Inventor： Wen-Yi Lin ,  Ming-Chih Yew ,  Po-Yao Lin ,  Jing Ruei Lu ,  Jiun Yi Wu

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L25/50 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17519 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package on packaging structure provides for improved thermal conduction and mechanical strength by the introduction of a sold thermal coupler between the first and second packages. The first package has a first substrate and through vias through the first substrate. A first set of conductive elements is aligned with and coupled to the through vias of the first substrate. A solid thermal coupler is coupled to the first set of conductive elements and to a die of the second package. A second set of conductive elements is coupled to the die and a bottom substrate is coupled to the second set of conductive elements. The thermal coupler may be, e.g., an interposer, a heat spreader, or a thermal conductive layer.

公开(公告)号：US20130075889A1

公开(公告)日：2013-03-28

申请号：US13244273

申请日：2011-09-23

Applicant: Byung Tai Do ,  Linda Pei Ee Chua

Inventor： Reza Argenty Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC: H01L23/34 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting a device mounting structure over a bottom substrate; mounting a heat spreader having an opening formed by a single integral structure with a dam and a flange, the dam having a dam height greater than a flange height of the flange; and forming a package encapsulation over the device mounting structure and the bottom substrate with the device mounting structure exposed within the opening.

Abstract translation: 集成电路封装系统的制造方法包括：将器件安装结构安装在底部衬底上; 安装具有由坝和法兰形成的具有单一整体结构的开口的散热器，所述坝具有大于所述凸缘的凸缘高度的坝高度; 以及在器件安装结构和底部衬底之间形成封装封装，其中器件安装结构暴露在开口内。

公开(公告)号：US20130069218A1

公开(公告)日：2013-03-21

申请号：US13237694

申请日：2011-09-20

Applicant: Lee Hua Alvin Seah

Inventor： Lee Hua Alvin Seah

IPC: H01L23/34 ,  H01L21/56 ,  H01L21/52

CPC classification number: H01L25/03 ,  H01L23/13 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1017 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2225/1094 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/1515 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00012

Abstract: The integrated circuit packaging techniques of the disclosed embodiments utilize a thermally conductive heat sink to partially enclose an integrated circuit. The heat sink is separated from the integrated circuit by a substrate that is conformally positioned into a recess in the heat sink, enabling the heat sink to transfer thermal energy from the integrated circuit.

Abstract translation: 所公开的实施例的集成电路封装技术利用导热散热器部分地封装集成电路。 散热器通过基体共面地与集成电路分离，该基板被共形地定位在散热器中的凹槽中，使散热片能够从集成电路传递热能。

公开(公告)号：US20130043587A1

公开(公告)日：2013-02-21

申请号：US13584027

申请日：2012-08-13

Applicant: Huahung Kao ,  Shiann-Ming Liou

Inventor： Huahung Kao ,  Shiann-Ming Liou

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3128 ,  H01L24/04 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/838 ,  H01L2224/92247 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls.

Abstract translation: 本公开的实施例提供了一种包装装置，包括底部包装和第二包装。 第一包装包括基底层，其包括（i）顶侧和（ii）与顶侧相对的底侧。 此外，顶侧限定基本平坦的表面。 第一封装还包括耦合到衬底层的底侧的管芯。 第二封装包括多排焊球，并且第二封装通过多排焊球附接到基板层的基本上平坦的表面。

公开(公告)号：US08379406B2

公开(公告)日：2013-02-19

申请号：US13035503

申请日：2011-02-25

Applicant: Heung Ku Kim

Inventor： Heung Ku Kim

IPC: H01R11/12

CPC classification number: H01L23/49816 ,  H01L23/481 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  Y10T29/49002

Abstract: Disclosed herein are a package and a method for manufacturing the same. The package includes: a first package including a first printed circuit board having a first surface and a second surface and having a first die mounted on the first surface, the first die having a through silicon via; a second package including a second printed circuit board having a first surface and a second surface and having a second die mounted on the first surface, the second die having a through silicon via; first external connecting terminals electrically interconnecting the first surface of the first printed circuit and the first surface of the second printed circuit disposed to be opposite to each other; and first connecting bumps electrically interconnecting the first and second dice. Therefore, power signals are independently applied to each of the dice, thereby making it possible to improve power stability of each of the dice.

Abstract translation: 本文公开了一种包装及其制造方法。 所述封装包括：第一封装，包括具有第一表面和第二表面的第一印刷电路板，并且具有安装在所述第一表面上的第一裸片，所述第一裸片具有硅通孔; 第二封装，包括具有第一表面和第二表面的第二印刷电路板，并且具有安装在所述第一表面上的第二管芯，所述第二管芯具有通过硅通孔; 第一外部连接端子将第一印刷电路的第一表面和彼此相对布置的第二印刷电路的第一表面电连接; 以及将所述第一和第二裸片电连接的第一连接凸块。 因此，功率信号被独立地施加到每个骰子，从而可以提高每个骰子的功率稳定性。

公开(公告)号：US20130037936A1

公开(公告)日：2013-02-14

申请号：US13208027

申请日：2011-08-11

Applicant: DaeSik Choi ,  YeongIm Park ,  HyungMin Lee

Inventor： DaeSik Choi ,  YeongIm Park ,  HyungMin Lee

IPC: H01L21/50 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L21/565 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/01082 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a substrate and first semiconductor die to the substrate. A plurality of vertically-oriented discrete electrical devices, such as a capacitor, inductor, resistor, diode, or transistor, is mounted over the substrate in proximity to the first semiconductor die. A first terminal of the discrete electrical devices is connected to the substrate. A plurality of bumps is formed over the substrate adjacent to the discrete electrical devices. An encapsulant is deposited over and between the first semiconductor die and substrate. A portion of the bumps and a second terminal of the discrete electrical devices is exposed from the encapsulant. An interconnect structure is formed over a surface of the substrate opposite the first semiconductor die. The semiconductor devices are stackable and electrically connected through the substrate, discrete electrical devices, and bumps. A heat spreader or second semiconductor die can be disposed between the stacked semiconductor devices.

Abstract translation: 半导体器件具有衬底和第一半导体管芯到衬底。 多个垂直取向的分立电气装置，例如电容器，电感器，电阻器，二极管或晶体管，安装在靠近第一半导体管芯的衬底上。 分立电气设备的第一端子连接到基板。 在与分立电气装置相邻的衬底上形成多个凸块。 密封剂沉积在第一半导体管芯和衬底之上和之间。 凸块的一部分和离散电气装置的第二端子从密封剂暴露出来。 在与第一半导体管芯相对的衬底的表面上形成互连结构。 半导体器件可堆叠并通过衬底电连接，分立的电子器件和凸块。 散热器或第二半导体管芯可以设置在堆叠的半导体器件之间。

公开(公告)号：US20130026650A1

公开(公告)日：2013-01-31

申请号：US13556448

申请日：2012-07-24

Applicant: Osamu Yamagata ,  Akio Katsumata ,  Hiroshi Inoue ,  Shigenori Sawachi ,  Satoru Itakura ,  Yasuhiro Yamaji

Inventor： Osamu Yamagata ,  Akio Katsumata ,  Hiroshi Inoue ,  Shigenori Sawachi ,  Satoru Itakura ,  Yasuhiro Yamaji

IPC: H01L23/48 ,  H01L21/50 ,  H01L21/78

CPC classification number: H01L24/97 ,  H01L24/19 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24226 ,  H01L2224/2518 ,  H01L2224/29099 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/0951 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/1579 ,  H01L2924/15798 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2924/00

Abstract: A semiconductor device is made up of an organic substrate; through vias which penetrate the organic substrate in its thickness direction; external electrodes and internal electrodes provided to the front and back faces of the organic substrate and electrically connected to the through vias; a semiconductor element mounted on one main surface of the organic substrate via a bonding layer, with an element circuit surface thereof facing upward; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part of this metal thin film wiring layer being exposed on an external surface; metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer; and external electrodes formed on the metal thin film wiring layer.

Abstract translation: 半导体器件由有机基片构成; 贯穿有机基板的厚度方向的通孔; 外部电极和内部电极，设置在有机基板的前表面和后表面上并电连接到通孔; 半导体元件经由接合层安装在有机基板的一个主表面上，其元件电路表面朝上; 用于密封半导体元件的绝缘材料层及其周边; 设置在所述绝缘材料层中的金属薄膜布线层，所述金属薄膜布线层的一部分露出在外表面上; 金属通孔，设置在绝缘材料层中并电连接到金属薄膜布线层; 以及形成在金属薄膜布线层上的外部电极。

公开(公告)号：US20120299173A1

公开(公告)日：2012-11-29

申请号：US13446874

申请日：2012-04-13

Applicant: Anwar A. Mohammed ,  Weifeng Liu

Inventor： Anwar A. Mohammed ,  Weifeng Liu

IPC: H01L23/34 ,  H01L21/50

CPC classification number: H01L23/373 ,  H01L23/3677 ,  H01L23/49816 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1515 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/16195 ,  H01L2924/00

Abstract: A package-on-package (PoP) device is provided. The device includes a first package with a first chip mounted on a first substrate, a heat spreader stacked on the first package, the heat spreader in thermal contact with the first chip, and a second package stacked on the heat spreader. In an embodiment, the heat spreader is formed using carbon fibers to provide good lateral thermal conductivity. In an embodiment, ends of the heat spreader project beyond a periphery of the first and second packages.

Abstract translation: 提供封装封装（PoP）器件。 该装置包括第一封装，其具有安装在第一基板上的第一芯片，堆叠在第一封装上的散热器，与第一芯片热接触的散热器以及堆叠在散热器上的第二封装。 在一个实施例中，散热器使用碳纤维形成以提供良好的横向导热性。 在一个实施例中，散热器的端部突出超过第一和第二封装的外围。

公开(公告)号：US08310038B2

公开(公告)日：2012-11-13

申请号：US13070219

申请日：2011-03-23

Applicant: JinGwan Kim ,  KyuWon Lee ,  JiHoon Oh ,  JongVin Park

Inventor： JinGwan Kim ,  KyuWon Lee ,  JiHoon Oh ,  JongVin Park

IPC: H01L21/10

CPC classification number: H01L23/552 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package carrier; mounting an integrated circuit device to the package carrier; mounting an embeddable conductive structure, having a non-horizontal portion between a lower portion and an elevated portion and a hole, to the integrated circuit device with the lower portion over the integrated circuit device; mounting an interposer to the lower portion and below the elevated portion; and forming an encapsulation having a recess exposing the interposer and the elevated portion.

Abstract translation: 一种集成电路封装系统的制造方法，包括：提供封装载体; 将集成电路器件安装到封装载体上; 在所述集成电路装置的下部安装具有在下部和升高部分之间的非水平部分和可以插入到所述集成电路装置的嵌入式导电结构; 将插入件安装到下部并在升高部分下方; 以及形成具有露出所述插入件和所述升高部分的凹部的封装。

公开(公告)号：US08269326B2

公开(公告)日：2012-09-18

申请号：US13043037

申请日：2011-03-08

Applicant: Teck Kheng Lee

Inventor： Teck Kheng Lee

IPC: H01L23/495 ,  H01L23/367 ,  H01L23/433 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/4334 ,  H01L23/3677 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An interposer includes a substrate, a conductive structure configured to contact the back side of a semiconductor device and contact pads. The interposer may include first and second sets of contact pads carried by the substrate. The interposer may also include conductive traces carried by the substrate to electrically connect corresponding contact pads of the first and second sets. The receptacles, which may be formed in a surface of the substrate and expose contacts of the second set, may be configured to at least partially receive conductive structures that are secured to the contact pads of the second set. Thus, the interposer may be useful in providing semiconductor device assemblies and packages of reduced height or profile. Such assemblies and packages are also described, as are multi-chip modules including such assemblies or packages. In addition, methods for designing and fabricating the interposer are disclosed, as are methods for forming assemblies, packages, and multi-chip modules that include the interposer.

Abstract translation: 插入器包括衬底，被配置为接触半导体器件的背面的导电结构和接触焊盘。 插入器可以包括由衬底承载的第一组和第二组接触垫。 插入器还可以包括由衬底承载的导电迹线以电连接第一和第二组的对应的接触垫。 可以形成在基板的表面中并暴露第二组的触点的插座可以被配置为至少部分地接收固定到第二组的接触垫的导电结构。 因此，插入器可用于提供减小高度或轮廓的半导体器件组件和封装。 还描述了这样的组件和封装，以及包括这种组件或封装的多芯片模块。 此外，公开了用于设计和制造插入器的方法，以及用于形成包括插入件的组件，封装和多芯片模块的方法。